A novel approach for implementing ultra-high speed flash ADC using MCML circuits
暂无分享,去创建一个
[1] Pedro M. Figueiredo,et al. Low kickback noise techniques for CMOS latched comparators , 2004, 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512).
[2] Kyusun Choi,et al. Fat tree encoder design for ultra-high speed flash A/D converters , 2002, The 2002 45th Midwest Symposium on Circuits and Systems, 2002. MWSCAS-2002..
[3] Jan M. Rabaey,et al. MOS current mode logic for low power, low noise CORDIC computation in mixed-signal environments , 2000, ISLPED'00: Proceedings of the 2000 International Symposium on Low Power Electronics and Design (Cat. No.00TH8514).
[4] Masakazu Yamashina,et al. An MOS Current Mode Logic (MCML) Circuit for Low-Power Sub-GHz Processors , 1992 .
[5] K. Uyttenhove,et al. A 1.8-V 6-bit 1.3-GHz flash ADC in 0.25-μm CMOS , 2003, IEEE J. Solid State Circuits.
[6] A.A. Abidi,et al. A 300 MHz mixed-signal FDTS/DFE disk read channel in 0.6 /spl mu/m CMOS , 2001, 2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177).
[7] Hui Pan,et al. Spatial filtering in flash A/D converters , 2003 .
[8] Behzad Razavi,et al. Principles of data conversion system design / Behzad Razavi , 1995 .
[9] J. A. Wepman,et al. Analog-to-digital converters and their applications in radio receivers , 1995, IEEE Commun. Mag..
[10] Martin Margala,et al. 6-bit low power low area frequency modulation based flash ADC , 2004, 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512).
[11] M. Vertregt,et al. A 6b 1.6GSample/s flash ADC in 0.18/spl mu/m CMOS using averaging termination , 2002 .