FPGA Implementation of an Area Efficient Matrix Code with Encoder Reuse Method

Area overhead is one of the major factors in memory protection schemes for multiple bit upsets. This paper deals with FPGA implementation of an area efficient Matrix code (MC). A fair comparison of area overhead, power and delay of MC has been made with Decimal Matrix code (DMC), Reed Muller code (RMC) and Hamming code (HC). MC has been implemented with encoder reuse architecture. Fault detection technique for encoder and decoder are also incorporated apart from memory protection using hardware redundancy. Correction coverage of MC, DMC, RMC and HC has been determined by injecting errors in random positions. The results show that Matrix code corrects errors with less area overhead compared to Decimal Matrix code, Reed Muller code and Hamming code.