Off-Chip Memory Traffic Measurements of Low-Power Embedded Systems

In all processors, power can be saved by making effective use of on-chip memory. For embedded systems this is crucial, since they often drain their power from a pair of batteries. In this paper, we experimentally measure the amount of off-chip traffic produced by several caches. It is shown that large savings can be achieved if size, associativity, and block size are well-chosen. Most examined directmapped caches produce five to ten times as much traffic as needed, but sometimes much more. For most benchmarks the minimum cache size to perform well is 8 kB. Overall, the results indicate that cost-effective on-chip caches are highly application-specific. Keywords— memory traffic; embedded systems; caches; power consumption