The physical and electrical effects of metal-fill patterning practices for oxide chemical-mechanical polishing processes

In oxide chemical-mechanical polishing (CMP) processes, layout pattern dependent variation in the interlevel dielectric (ILD) thickness can reduce yield and impact circuit performance. Metal-fill patterning practices have emerged as a technique for substantially reducing layout pattern dependent ILD thickness variation. We present a generalizable methodology for selecting an optimal metal-fill patterning practice with the goal of satisfying a given dielectric thickness variation specification while minimizing the added interconnect capacitance associated with metal-fill patterning. Data from two industrial-based experiments demonstrate the beneficial impact of metal-fill on dielectric thickness variation, a 20% improvement in uniformity in one case and a 60% improvement in the other case, and illustrate that pattern density is the key mechanism involved. The pros and cons of two different metal-fill patterning practices-grounded versus floating metal-are explored. Criteria for minimizing the effect of floating or grounded metal-fill patterns on delay or crosstalk parameters are also developed based on canonical metal-fill structures. Finally, this methodology is illustrated using a case study which demonstrates an 82% reduction in ILD thickness variation.

[1]  J. G. Ryan,et al.  Dual Damascene: a ULSI wiring technology , 1991, 1991 Proceedings Eighth International IEEE VLSI Multilevel Interconnection Conference.

[2]  Jacob K. White,et al.  FastCap: a multipole accelerated 3-D capacitance extraction program , 1991, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[3]  P. A. Burke.  Semi-Empirical Modelling of Si02 Chemical-Mechanical Polishing: Planarization , 1991 .

[4]  P. A. Burke.  Semi-empirical modelling of SiO/sub 2/ chemical-mechanical polishing planarization , 1991, 1991 Proceedings Eighth International IEEE VLSI Multilevel Interconnection Conference.

[5]  Wojciech Maly,et al.  Memory chip for 24-port global register file , 1991, Proceedings of the IEEE 1991 Custom Integrated Circuits Conference.

[6]  Robert D. Tolles,et al.  Planarizing interlevel dielectrics by chemical-mechanical polishing , 1992 .

[7]  Robert D. Tolles,et al.  Chemical Mechanical Polishing of Interlevel Dielectrics: Models for Removal Rate and Planarity , 1992 .

[8]  I. Ali,et al.  Chemical-mechanical polishing of interlayer dielectric: a review , 1994 .

[9]  Andres Bryant,et al.  Characteristics of CMOS device isolation for the ULSI age , 1994, Proceedings of 1994 IEEE International Electron Devices Meeting.

[10]  L. E. Camilletti.  Implementation of CMP-based design rules and patterning practices , 1995, Proceedings of SEMI Advanced Semiconductor Manufacturing Conference and Workshop.

[11]  M. Fury.  Emerging developments in CMP for semiconductor planarization , 1995 .

[12]  Duane S. Boning,et al.  Using a statistical metrology framework to identify systematic and random sources of die- and wafer-level ILD thickness variation in CMP processes , 1995, Proceedings of International Electron Devices Meeting.

[13]  A. Perera,et al.  Trench isolation for 0.45 /spl mu/m active pitch and below , 1995, Proceedings of International Electron Devices Meeting.

[14]  Duane S. Boning,et al.  A CLOSED-FORM ANALYTIC MODEL FOR ILD THICKNESS VARIATION IN CMP PROCESSES , 1997 .

[15]  O. S. Nakagawa,et al.  Rapid characterization and modeling of pattern-dependent variation in chemical-mechanical polishing , 1998 .

[16]  Duane S. Boning,et al.  Assessing and characterizing inter-and intra-die variation using a statistical metrology framework: A CMP case study , 1999 .