Effective capacitance of RLC loads for estimating short-circuit power

An effective capacitance of a distributed RLC load for estimating short-circuit power is presented in this paper. Both resistive and inductive shielding effects of interconnects are considered and no iterations are required to determine the effective capacitance. The proposed method has been verified with Cadence Spectre. For a single switching input, the average error of the short-circuit power obtained with the effective capacitance is less than 2% for the example circuits as compared with an RLC pi model. The proposed method can be used in look-up table or k-factor based models to estimate short-circuit power dissipation in CMOS gates with complex interconnects

[1]  Takayasu Sakurai,et al.  Analysis and future trend of short-circuit power , 2000, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[2]  Hendrikus J. M. Veendrick,et al.  Short-circuit dissipation of static CMOS circuitry and its impact on the design of buffer circuits , 1984 .

[3]  Eby G. Friedman,et al.  Shielding effect of on-chip interconnect inductance , 2003, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[4]  Sarma Vrudhula,et al.  A new short circuit power model for complex CMOS gates , 1999, Proceedings IEEE Alessandro Volta Memorial Workshop on Low-Power Design.

[5]  Jaume Segura,et al.  Charge-based analytical model for the evaluation of powerconsumption in submicron CMOS buffers , 2002, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[6]  Chung-Kuan Cheng,et al.  Hurwitz stable reduced order modeling for RLC interconnect trees , 2000, IEEE/ACM International Conference on Computer Aided Design. ICCAD - 2000. IEEE/ACM Digest of Technical Papers (Cat. No.00CH37140).

[7]  Lawrence T. Pileggi,et al.  Modeling the "Effective capacitance" for the RC interconnect of CMOS gates , 1994, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[8]  Alexander Chatzigeorgiou,et al.  Modeling CMOS gates driving RC interconnect loads , 2001 .

[9]  Guoqing Chen,et al.  An RLC interconnect model based on fourier analysis , 2005, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[10]  Lawrence T. Pileggi,et al.  Performance computation for precharacterized CMOS gates with RC loads , 1996, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[11]  P. R. O'Brien,et al.  Modeling the driving-point characteristic of resistive interconnect for accurate delay estimation , 1989, ICCAD 1989.

[12]  Yehea Ismail,et al.  Figures of merit to characterize the importance of on-chip inductance , 1999 .