A 2.4-GHz Subharmonically Injection-Locked PLL With Self-Calibrated Injection Timing

A 2.4-GHz subharmonically injection-locked PLL (SILPLL) with injection timing calibration is realized. The injection timing issues has been clearly described and modeled mathematically. An injection timing calibration technique is presented to ensure the best phase noise performance. This work is fabricated in 0.18-μm process with 12.6-mW power consumption. The measured phase noises at 1 MHz offset before and after injection are -114 and -129 dBc/Hz, respectively. The measured rms jitter integrated from 1 kHz to 40 MHz before and after injection are 317 and 145 fs, respectively.

[1]  Che-Fu Liang,et al.  An injection-locked ring PLL with self-aligned injection window , 2011, 2011 IEEE International Solid-State Circuits Conference.

[2]  R. Farjad-Rad,et al.  A 0.2-2 GHz 12 mW multiplying DLL for low-jitter clock synthesis in highly-integrated data communication chips , 2002, 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315).

[3]  B.M. Helal,et al.  A Highly Digital MDLL-Based Clock Multiplier That Leverages a Self-Scrambling Time-to-Digital Converter to Achieve Subpicosecond Jitter Performance , 2008, IEEE Journal of Solid-State Circuits.

[4]  Eric A. M. Klumperink,et al.  A 2.2GHz 7.6mW sub-sampling PLL with −126dBc/Hz in-band phase noise and 0.15psrms jitter in 0.18µm CMOS , 2009, 2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

[5]  Eric A. M. Klumperink,et al.  2 A 2 . 2 GHz 7 . 6 mW SubSampling PLL with − 126 dBc / Hz In-Band Phase Noise and 0 . 15 psrms Jitter in 0 . 18 μ m CMOS , 2009 .

[6]  Eric A. M. Klumperink,et al.  Jitter Analysis and a Benchmarking Figure-of-Merit for Phase-Locked Loops , 2009, IEEE Transactions on Circuits and Systems II: Express Briefs.

[7]  Ron Ho,et al.  A 4.6GHz MDLL with −46dBc reference spur and aperture position tuning , 2011, 2011 IEEE International Solid-State Circuits Conference.

[8]  B. Helal,et al.  A Low Jitter Programmable Clock Multiplier Based on a Pulse Injection-Locked Oscillator With a Highly-Digital Tuning Loop , 2008, IEEE Journal of Solid-State Circuits.

[9]  Bram Nauta,et al.  A 2.2GHz sub-sampling PLL with 0.16psrms jitter and −125dBc/Hz in-band phase noise at 700µW loop-components power , 2010, 2010 Symposium on VLSI Circuits.

[10]  Jri Lee,et al.  Study of Subharmonically Injection-Locked PLLs , 2009, IEEE Journal of Solid-State Circuits.

[11]  Sheng Ye,et al.  A multiple-crystal interface PLL with VCO realignment to reduce phase noise , 2002, 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315).

[12]  A.A. Abidi,et al.  A 9 b, 1.25 ps Resolution Coarse–Fine Time-to-Digital Converter in 90 nm CMOS that Amplifies a Time Residue , 2008, IEEE Journal of Solid-State Circuits.