论文信息 - A sub 100ns static 64k CMOS EPROM with on-chip test functions

A sub 100ns static 64k CMOS EPROM with on-chip test functions

This report will cover the design of a sub 100ns 64K N-well CMOS EPROM with 1μW quiescent power dissipation. On-chip test circuits have been used to reduce the time required for testing and reliability screening. Typical access time is 80ns.

P. Keshtbod | M. Knecht | G. Simmons | M. Manley

[1] K.C. Hardee,et al. A fault-tolerant 30 ns/375 mW 16Kx1 NMOS static RAM , 1981, IEEE Journal of Solid-State Circuits.

[2] Mitsuo Higuchi,et al. A 150ns CMOS 64K EPROM using N-well technology , 1982 .