Demonstration of speed enhancements on an industrial circuit through application of non-zero clock skew scheduling

A demonstration of the application of non-zero clock skew scheduling to enhance the speed characteristics of several functional unit blocks in a high performance processor is presented. It is shown that non-zero clock skew scheduling can improve circuit performance while relaxing the strict timing constraints of the critical data paths within a high speed system. A software tool implementing a non-zero clock skew scheduling algorithm is described together with a methodology that generates the required clock signal delays by replacing clock buffers from predesigned cell libraries. Timing margin improvements of up to 18% are achieved through the application of non-zero clock skew scheduling in certain functional blocks of an industrial high performance microprocessor.

[1]  John P. Fishburn,et al.  Clock Skew Optimization , 1990, IEEE Trans. Computers.

[2]  A. Kahng,et al.  On optimal interconnections for VLSI , 1994 .

[3]  G. G. Stokes.  "J." , 1890, The New Yale Book of Quotations.

[4]  Jan-Ming Ho,et al.  Zero skew clock routing with minimum wirelength , 1992 .

[5]  Eby G. Friedman,et al.  Clock skew scheduling for improved reliability via quadratic programming , 1999, 1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051).

[6]  Ji Zhang,et al.  Itanium processor clock design , 2000, ISPD '00.

[7]  Eby G. Friedman,et al.  Repeater design to reduce delay and power in resistive interconnect , 1998 .

[8]  Eby G. Friedman,et al.  Optimal clock skew scheduling tolerant to process variations , 1996, DAC '96.

[9]  Eby G. Friedman,et al.  Design methodology for synthesizing clock distribution networks exploiting nonzero localized clock skew , 1996, IEEE Trans. Very Large Scale Integr. Syst..

[10]  Eby G. Friedman,et al.  Buffered Clock Tree Synthesis with Non-Zero Clock Skew Scheduling for Increased Tolerance to Process Parameter Variations , 1997, J. VLSI Signal Process..

[11]  E. G. Friedman,et al.  Synthesis of clock tree topologies to implement nonzero clock skew schedule , 1999 .

[12]  Baris Taskin,et al.  Timing Optimization Through Clock Skew Scheduling , 2000 .

[13]  Eby G. Friedman,et al.  Demonstration of Speed and Power Enhancements through Application of Non-Zero Clock Skew Scheduling , 2000 .

[14]  Eby G. Friedman,et al.  Design and analysis of a hierarchical clock distribution system for synchronous standard cell/macrocell VLSI , 1986 .

[15]  Eby G. Friedman.  Clock distribution networks in VLSI circuits and systems , 1995 .

[16]  S. Tam,et al.  Clock generation and distribution for the first IA-64 microprocessor , 2000, 2000 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.00CH37056).