An Efficient All-Digital Phase-Locked Loop with Input Fault Detection

An all-digital phase-locked loop (ADPLL) having a fault detection of the input reference signal was modeled in Verilog hardware descriptive language (HDL) and is presented in this paper. The design can track an input signal with frequency ranging from 61kHz to 43MHz in a maximum locked-in time of five reference cycles. In the case of loss of input reference, it can continue to generate an output signal with the previously stored parameters and report the anomaly as status. The functional and timing requirements of the design were verified using Synopsys electronic design automation (EDA) tools. The ADPLL can be utilized as an intellectual property (IP) core to reduce the development time of an application-specified integrated circuit (ASIC) product. The input fault monitoring capability can provide operational feedback that improves the overall system reliability.

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