In this paper, we discuss a technique for selective GeO<inf>x</inf>-scavenging which creates a GeO<inf>x</inf>-free interfacial layer (IL) on Si<inf>1−x</inf>Ge<inf>x</inf> substrates. This process reduces interface trap density (N<inf>it</inf>) and increases high-field hole mobility in Si<inf>1−x</inf>Ge<inf>x</inf> pFETs. In addition, we identify the existence of electronic defect levels close to the Si<inf>1−x</inf>Ge<inf>x</inf> band edges associated with the Ge surface concentration at the Si<inf>1−x</inf>Ge<inf>x</inf>/IL interface. These electronic defects act as carrier scattering centers severely degrading the channel mobility and modulate the device threshold voltage. By successfully eliminating the GeO<inf>x</inf> component in the IL and electronic defects states at the Si<inf>1−x</inf>Ge<inf>x</inf>/IL interface, high channel carrier mobility over a wide range of inversion carrier density in compressively-strained Si<inf>1−x</inf>Ge<inf>x</inf> channel pFETs is demonstrated.