Gate coupled NMOS power clamp protection circuit based on PD SOI technology

With the quick development of silicon-on-insulator(SOI) technology,electro static dischargs(ESD) protection of SOI integrated circuit is becoming a major reliability issue.In order to form whole-chip ESD protection network,this paper investigates the gate coupled N metal oxide semiconductor(GCNMOS) power clamp protection circuit based on partially depleted(PD) SOI technology.The values of resistance and capacitance can be accurately determined by HSPICE simulation method so that the gate voltage of NMOS can be coupled to a reasonable value.According to the PD SOI technology characteristic,GCNMOS power clamp circuits with different body bias,different implant type and different width are designed and fabricated.On the basis of transmission line pulse(TLP) measured results and analysis,gate coupled circuit composed of H gate NMOS with body floating and deep implant drain and source has the best robustness level,that is,the anti-human body model(HBM) ESD capability can be as high as 9.25 V/μm.