Bee Colony Inspired Metamodeling Based Fast Optimization of a Nano-CMOS PLL

The design and optimization complexity of analog/mixed-signal (AMS) components causes significant increase in the design cycle as the technology progresses towards deep nanoscale. This paper presents a two-tier approach to significantly reduce the design cycle time by combining accurate metamodeling and intelligent optimization. The paper first presents metamodeling which is a surrogate model of a parasitic-aware SPICE model of the circuit in order to simplify the optimization calculations and minimize the design space exploration time. The paper then introduces the Bee Colony Optimization (BCO) algorithm for nano-CMOS AMS circuit optimization. To best of the authors' knowledge, this is the first research combining metamodel and BCO for AMS design space exploration. The proposed design optimization flow is used on 5 metamodels with 21 design parameters each, corresponding to 5 distinct Figures of Merit (FoMs) to conduct multi objective optimization. A 180 nm LC-VCO PLL frequency generation circuit is used as case study. The optimization achieved approx. 90% power and 52% jitter reduction while keeping locking time constraints on the system. In comparison to an exhaustive simulation approach, metamodeling is 10^20 times faster.

[1]  David J. Allstot,et al.  NSGA-based parasitic-aware optimization of a 5GHz low-noise VCO , 2004 .

[2]  Wei Dong,et al.  Efficient VCO phase macromodel generation considering statistical parametric variations , 2007, 2007 IEEE/ACM International Conference on Computer-Aided Design.

[3]  Pavan Kumar Hanumolu,et al.  Analysis of charge-pump phase-locked loops , 2004, IEEE Transactions on Circuits and Systems I: Regular Papers.

[4]  Mohammad-Taghi Vakil-Baghmisheh,et al.  Discrete bee algorithms and their application in multivariable function optimization , 2010, Artificial Intelligence Review.

[5]  L. Balewski,et al.  Towards automated full-wave design of microwave circuits , 2008, MIKON 2008 - 17th International Conference on Microwaves, Radar and Wireless Communications.

[6]  Jean-Olivier Plouchart,et al.  CMOS Mixed-Signal Circuit Process Variation Sensitivity Characterization for Yield Improvement , 2006, IEEE Custom Integrated Circuits Conference 2006.

[7]  Robert V. Brill,et al.  Applied Statistics and Probability for Engineers , 2004, Technometrics.

[8]  Saraju P. Mohanty,et al.  Design of Parasitic and Process-Variation Aware Nano-CMOS RF Circuits: A VCO Case Study , 2009, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[9]  Charlie Chung-Ping Chen,et al.  SmartSmooth: A linear time convexity preserving smoothing algorithm for numerically convex data with application to VLSI design , 2007, 2007 Asia and South Pacific Design Automation Conference.

[10]  Dervis Karaboga,et al.  A powerful and efficient algorithm for numerical function optimization: artificial bee colony (ABC) algorithm , 2007, J. Glob. Optim..

[11]  Alex Doboli,et al.  Exploration-based high-level synthesis of linear analog systems operating at low/medium frequencies , 2003, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[12]  Kiyong Choi,et al.  Parasitic-aware design and optimization of a fully integrated CMOS wideband amplifier , 2003, ASP-DAC '03.

[13]  Saraju P. Mohanty,et al.  Fast optimization of nano-CMOS mixed-signal circuits through accurate metamodeling , 2011, 2011 12th International Symposium on Quality Electronic Design.

[14]  Reza Akbari,et al.  A multi-objective Artificial Bee Colony for optimizing multi-objective problems , 2010, 2010 3rd International Conference on Advanced Computer Theory and Engineering(ICACTE).

[15]  Malcolm Yoke-Hean Low,et al.  A Bee Colony Optimization Algorithm to Job Shop Scheduling , 2006, Proceedings of the 2006 Winter Simulation Conference.

[16]  H.C. Luong,et al.  Ultra-low-Voltage high-performance CMOS VCOs using transformer feedback , 2005, IEEE Journal of Solid-State Circuits.

[17]  S. Andersson,et al.  On the power consumption of analog to digital converters , 2006, 2006 NORCHIP.

[18]  Ranga Vemuri,et al.  Variation-Aware Macromodeling and Synthesis of Analog Circuits Using Spline Center and Range Method and Dynamically Reduced Design Space , 2009, 2009 22nd International Conference on VLSI Design.

[19]  Deepak Mathaikutty,et al.  Metamodeling Driven IP Reuse for System-on-chip Integration and Microprocessor Design , 2007 .

[20]  Ranga Vemuri,et al.  Accuracy driven performance macromodeling of feasible regions during synthesis of analog circuits , 2005, GLSVLSI '05.

[21]  P. Lucic,et al.  Bee Colony Optimization: Principles and Applications , 2006, 2006 8th Seminar on Neural Network Applications in Electrical Engineering.

[22]  Saraju P. Mohanty,et al.  Nano-CMOS Mixed-Signal Circuit Metamodeling Techniques: A Comparative Study , 2010, 2010 International Symposium on Electronic System Design.

[23]  Zuoding Wang.  An analysis of charge-pump phase-locked loops , 2005, IEEE Transactions on Circuits and Systems I: Regular Papers.

[24]  Ranga Vemuri,et al.  Efficient Synthesis of a Uniformly Spread Layout Aware Pareto Surface for Analog Circuits , 2009, 2009 22nd International Conference on VLSI Design.

[25]  Peng Li,et al.  Discrete Buffer and Wire Sizing for Link-Based Non-Tree Clock Networks , 2008, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[26]  Azadeh Davoodi,et al.  A statistical methodology for wire-length prediction , 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[27]  Ranga Vemuri,et al.  Extraction and use of neural network models in automated synthesis of operational amplifiers , 2003, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..