Statistical Threshold-Voltage Variability in Scaled Decananometer Bulk HKMG MOSFETs: A Full-Scale 3-D Simulation Scaling Study

This paper presents a comprehensive full-scale three-dimensional simulation scaling study of the statistical threshold-voltage variability in bulk high-k/metal gate (HKMG) MOSFETs with gate lengths of 35, 25, 18, and 13 nm. Metal gate granularity (MGG) and corresponding workfunction-induced threshold-voltage variability have become important sources of statistical variability in bulk HKMG MOSFETs. It is found that the number of metal grains covering the gate plays an important role in determining the shape of the threshold-voltage distribution and the magnitude of the threshold-voltage variability in scaled devices in the presence of dominant variability sources (MGG, random discrete dopants, and line edge roughness). The placement of metal grains is found to also contribute to the total MGG variability. This paper presents the relative importance of MGG compared with other statistical variability sources. It is found that MGG can distort and even dominate the threshold-voltage statistical distribution when the metal grain size cannot be adequately controlled.

[1]  H. Wong,et al.  Three-dimensional "atomistic" simulation of discrete random dopant distribution effects in sub-0.1 /spl mu/m MOSFET's , 1993, Proceedings of IEEE International Electron Devices Meeting.

[2]  A. Toriumi,et al.  Experimental study of threshold voltage fluctuation due to statistical variation of channel dopant number in MOSFET's , 1994 .

[3]  K. Takeuchi,et al.  Channel engineering for the reduction of random-dopant-placement-induced threshold voltage fluctuation , 1997, International Electron Devices Meeting. IEDM Technical Digest.

[4]  Vivek De,et al.  Intrinsic MOSFET parameter fluctuations due to random dopant placement , 1997, IEEE Trans. Very Large Scale Integr. Syst..

[5]  P. Stolk,et al.  Modeling statistical dopant fluctuations in MOS transistors , 1998 .

[6]  The microstructure of transparent and electrically conducting titanium nitride films , 1998 .

[7]  A. Asenov Random dopant induced threshold voltage lowering and fluctuations in sub-0.1 /spl mu/m MOSFET's: A 3-D "atomistic" simulation study , 1998 .

[8]  M. Ieong,et al.  Monte Carlo modeling of threshold variation due to dopant fluctuations , 1999, 1999 Symposium on VLSI Circuits. Digest of Papers (IEEE Cat. No.99CH36326).

[9]  M. Ieong,et al.  Modeling line edge roughness effects in sub 100 nanometer gate length devices , 2000, 2000 International Conference on Simulation Semiconductor Processes and Devices (Cat. No.00TH8502).

[10]  Shoji Miyake,et al.  Structure refinement and hardness enhancement of titanium nitride films by addition of copper , 2001 .

[11]  Stergios Logothetidis,et al.  Optical, electronic, and transport properties of nanocrystalline titanium nitride thin films , 2001 .

[12]  Yoshitaka Tsunashima,et al.  Improvement of threshold voltage deviation in damascene metal gate transistors , 2001 .

[13]  Andrew R. Brown,et al.  Increase in the random dopant induced threshold fluctuations and lowering in sub-100 nm MOSFETs due to quantum effects: a 3-D density-gradient simulation study , 2001 .

[14]  T. Kudo,et al.  High performance 35 nm gate length CMOS with NO oxynitride gate dielectric and ni SALICIDE , 2001, International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224).

[15]  Andrew R. Brown,et al.  Analysis of Statistical Fluctuations due to Line Edge Roughness in sub-0.1μm MOSFETs , 2001 .

[16]  W. Sansen,et al.  Line edge roughness: characterization, modeling and impact on device behavior , 2002, Digest. International Electron Devices Meeting,.

[17]  A. Asenov,et al.  Intrinsic parameter fluctuations in decananometer MOSFETs introduced by gate line edge roughness , 2003 .

[18]  M. Hane,et al.  Atomistic 3D process/device simulation considering gate line-edge roughness and poly-Si random crystal orientation effects [MOSFETs] , 2003, IEEE International Electron Devices Meeting 2003.

[19]  Andrew R. Brown,et al.  Simulation of intrinsic parameter fluctuations in decananometer and nanometer-scale MOSFETs , 2003 .

[20]  J. Kavalieros,et al.  High-/spl kappa//metal-gate stack and its MOSFET characteristics , 2004, IEEE Electron Device Letters.

[21]  Suman Datta,et al.  High- /Metal-Gate Stack and Its MOSFET Characteristics , 2004 .

[22]  J. Bokor,et al.  A simulation study of gate line edge roughness effects on doping profiles of short-channel MOSFET devices , 2004, IEEE Transactions on Electron Devices.

[23]  N. Balasubramanian,et al.  Three-Layer laminated metal gate electrodes with tunable work functions for CMOS applications , 2005, IEEE Electron Device Letters.

[24]  Sylvain Maitrejean,et al.  Investigations of titanium nitride as metal gate material, elaborated by metal organic atomic layer deposition using TDMAT and NH3 , 2005 .

[25]  E. Cartier,et al.  Extremely scaled gate-first high-k/metal gate stack with EOT of 0.55 nm using novel interfacial layer scavenging techniques for 22nm technology node and beyond , 2006, 2009 Symposium on VLSI Technology.

[26]  A. Asenov,et al.  Impact of Fermi level pinning at polysilicon gate grain boundaries on nano-MOSFET variability: A 3-D simulation study , 2006, 2006 European Solid-State Device Research Conference.

[27]  A. Asenov,et al.  Simulation Study of Individual and Combined Sources of Intrinsic Parameter Fluctuations in Conventional Nano-MOSFETs , 2006, IEEE Transactions on Electron Devices.

[28]  Asen Asenov,et al.  Intrinsic parameter fluctuations due to random grain orientations in high-κ gate stacks , 2006 .

[29]  G. Bersuker,et al.  Gate first high-k/metal gate stacks with zero SiOx interface achieving EOT=0.59nm for 16nm application , 2006, 2009 Symposium on VLSI Technology.

[30]  K.J. Kuhn,et al.  Reducing Variation in Advanced Logic Technologies: Approaches to Process and Design for Manufacturability of Nanoscale CMOS , 2007, 2007 IEEE International Electron Devices Meeting.

[31]  A. Asenov,et al.  Poly-Si-Gate-Related Variability in Decananometer MOSFETs With Conventional Architecture , 2007, IEEE Transactions on Electron Devices.

[32]  R. Chau,et al.  A 45nm Logic Technology with High-k+Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100% Pb-free Packaging , 2007, 2007 IEEE International Electron Devices Meeting.

[33]  Sani R. Nassif,et al.  High Performance CMOS Variability in the 65nm Regime and Beyond , 2006, 2007 IEEE International Electron Devices Meeting.

[34]  Sani R. Nassif,et al.  High Performance CMOS Variability in the 65nm Regime and Beyond , 2007 .

[35]  Y. Nara,et al.  Impact of additional factors in threshold voltage variability of metal/high-k gate stacks and its reduction by controlling crystalline structure and grain size in the metal gates , 2008, 2008 IEEE International Electron Devices Meeting.

[36]  B. Cheng,et al.  Advanced simulation of statistical variability and reliability in nano CMOS transistors , 2008, 2008 IEEE International Electron Devices Meeting.

[37]  K. Banerjee,et al.  Statistical modeling of metal-gate Work-Function Variability in emerging device technologies and implications for circuit design , 2008, 2008 IEEE/ACM International Conference on Computer-Aided Design.

[38]  K. Banerjee,et al.  Modeling and analysis of grain-orientation effects in emerging metal-gate devices and implications for SRAM reliability , 2008, 2008 IEEE International Electron Devices Meeting.

[39]  A. Asenov,et al.  Accurate Statistical Description of Random Dopant-Induced Threshold Voltage Variability , 2008, IEEE Electron Device Letters.

[40]  A. Asenov,et al.  Quantitative Evaluation of Statistical Variability Sources in a 45-nm Technological Node LP N-MOSFET , 2008, IEEE Electron Device Letters.

[41]  Yiming Li,et al.  Random-Dopant-Induced Variability in Nano-CMOS Devices and Digital Circuits , 2009, IEEE Transactions on Electron Devices.

[42]  Y. Nishi,et al.  Physical model of the impact of metal grain work function variability on emerging dual metal gate MOSFETs and its implication for SRAM reliability , 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

[43]  A. Asenov,et al.  Analysis of Threshold Voltage Distribution Due to Random Dopants: A 100 000-Sample 3-D Simulation Study , 2009, IEEE Transactions on Electron Devices.

[44]  3D device simulation of work function and interface trap fluctuations on high-κ / metal gate devices , 2010, 2010 International Electron Devices Meeting.

[45]  Statistical simulation of metal-gate work-function fluctuation in high-κ/metal-gate devices , 2010, 2010 International Conference on Simulation of Semiconductor Processes and Devices.

[46]  D Reid,et al.  Understanding LER-Induced MOSFET $V_{T}$ Variability—Part I: Three-Dimensional Simulation of Large Statistical Samples , 2010, IEEE Transactions on Electron Devices.

[47]  Yiming Li,et al.  Process-Variation Effect, Metal-Gate Work-Function Fluctuation, and Random-Dopant Fluctuation in Emerging CMOS Technologies , 2010, IEEE Transactions on Electron Devices.

[48]  Andrew R. Brown,et al.  Impact of Metal Gate Granularity on Threshold Voltage Variability: A Full-Scale Three-Dimensional Statistical Simulation Study , 2010, IEEE Electron Device Letters.

[49]  Kazuhiko Endo,et al.  Grain-Orientation Induced Work Function Variation in Nanoscale Metal-Gate Transistors—Part I: Modeling, Analysis, and Experimental Validation , 2010, IEEE Transactions on Electron Devices.

[50]  Asen Asenov,et al.  Hierarchical Simulation of Statistical Variability: From 3-D MC With “ ab initio” Ionized Impurity Scattering to Statistical Compact Models , 2010, IEEE Transactions on Electron Devices.