Design of Comparator in Sigma-Delta ADC Using 45 nm CMOS Technology

An energy efficient comparator circuit for sigma-delta ADC has been proposed in this paper. The proposed comparator uses CMOS two-stage opamp. The designed opamp shows 89 dB gain, 2.3 GHz UGB, and 65o phase margin with 1.02 mW power dissipation. Both opamp and comparator output responses have been extracted from the circuit at ± 1 V operating voltage. The proposed circuit is simulated in Cadence Analog Design Environment with gpdk045 nm library. The comparator circuit has been designed such that the simulation result ranges between −100 and 500 mV.

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