60GHz power amplifier with distributed active transformer and local feedback

A 52–61 GHz power amplifier (PA) is implemented in 65nm CMOS bulk technology. The distributed active transformer (DAT) combines the output power from two unit PAs and achieves a peak output power of 14.8 dBm. Each unit PA uses two-stage differential cascode topology. This PA achieves a peak power gain of 10.2 dB with 10.8 dBm 1-dB compression output power (OP1dB) and a peak power-added efficiency (PAE) of 7.2%. The transformer based passives enable a compact active area of 0.3mm2. This PA consumes a quiescent current of 143mA from a 1.6V supply voltage. Thanks to the linearization of last stage, the OP1dB can be further improved to 11.8 dBm when the driver's supply voltage increases to 2.2V.

[1]  D. Rutledge,et al.  An optimized design of distributed active transformer , 2005, IEEE Transactions on Microwave Theory and Techniques.

[2]  P. Schvan,et al.  Algorithmic Design of CMOS LNAs and PAs for 60-GHz Radio , 2007, IEEE Journal of Solid-State Circuits.

[3]  T.S.D. Cheung,et al.  A 21-26-GHz SiGe bipolar power amplifier MMIC , 2005, IEEE Journal of Solid-State Circuits.

[4]  M. Feng,et al.  A RF CMOS amplifier with optimized gain, noise, linearity and return losses for UWB applications , 2008, 2008 IEEE Radio Frequency Integrated Circuits Symposium.

[5]  P. Reynaert,et al.  Design Considerations for 60 GHz Transformer-Coupled CMOS Power Amplifiers , 2009, IEEE Journal of Solid-State Circuits.