CMOS / CMOL architectures for spiking cortical column

We present a spiking cortical column model based on neural associative memory, and demonstrate architectures for emulating the cortical column model with nanogrid molecular circuitry. We investigate a number of options for cost-effective hardware with digital CMOS and mixed-signal CMOL, a hybrid CMOS/nanogrid technology. We also give an example of a dynamic learning algorithm that is a suitable match to CMOL implementation.

[1]  Changjian Gao,et al.  Cortical Models Onto CMOL and CMOS— Architectures and Performance/Price , 2007, IEEE Transactions on Circuits and Systems I: Regular Papers.

[2]  John Hallam,et al.  Marr's Theory of the Neocortex as a Self-Organizing Neural Network , 1997, Neural Computation.

[3]  Xiaolong Ma,et al.  Architectures for nanoelectronic implementation of artificial neural networks: new results , 2005, Neurocomputing.

[4]  D. Stewart,et al.  The crossbar latch: Logic value storage, restoration, and inversion in crossbar circuits , 2005 .

[5]  J J Hopfield,et al.  What is a moment? Transient synchrony as a collective mechanism for spatiotemporal integration. , 2001, Proceedings of the National Academy of Sciences of the United States of America.

[6]  Sander M. Bohte,et al.  Unsupervised clustering with spiking neurons by sparse temporal coding and multilayer RBF networks , 2002, IEEE Trans. Neural Networks.

[7]  Tim Schönauer,et al.  NeuroPipe-Chip: A digital neuro-processor for spiking neural networks , 2002, IEEE Trans. Neural Networks.

[8]  Giacomo Indiveri,et al.  A VLSI array of low-power spiking neurons and bistable synapses with spike-timing dependent plasticity , 2006, IEEE Transactions on Neural Networks.

[9]  Ulrich Rückert,et al.  Mixed Mode VLSI Implementation of a Neural Associative Memory , 1999 .

[10]  D. Strukov,et al.  CMOL: Devices, Circuits, and Architectures , 2006 .

[11]  William J. Dauksher,et al.  Imprint lithography for integrated circuit fabrication , 2003 .

[12]  Wulfram Gerstner,et al.  Spiking neurons , 1999 .

[13]  Ulrich Rückert.  An associative memory with neural architecture and its VLSI implementation , 1991 .

[14]  Alan F. Murray,et al.  Synchrony Detection by Analogue VLSI Neurons with Bimodal STDP Synapses , 2003, NIPS.

[15]  Kwabena Boahen,et al.  Point-to-point connectivity between neuromorphic chips using address events , 2000 .

[16]  Eugene M. Izhikevich,et al.  Polychronization: Computation with Spikes , 2006, Neural Computation.

[17]  Charles M. Lieber,et al.  Ge/Si nanowire heterostructures as high-performance field-effect transistors , 2006, Nature.

[18]  Ulrich Rückert,et al.  ULSI Architectures for Artificial Neural Networks , 2001, IEEE Micro.

[19]  Alan F. Murray,et al.  International Joint Conference on Neural Networks , 1993 .

[20]  Renato J. O. Figueiredo,et al.  Guest Editors' Introduction: Resource Virtualization Renaissance , 2005, Computer.

[21]  D. George,et al.  A hierarchical Bayesian model of invariant pattern recognition in the visual cortex , 2005, Proceedings. 2005 IEEE International Joint Conference on Neural Networks, 2005..

[22]  John E. Barth,et al.  Embedded DRAM: Technology platform for the Blue Gene/L chip , 2005, IBM J. Res. Dev..

[23]  M. J. Hudak.  RCE classifiers: theory and practice , 1992 .