Reliability of through-silicon-vias (TSVs) with benzocyclobutene liners

Abstract Through-silicon-vias (TSVs) using benzocyclobutene (BCB) as insulation layers (liners) are developed and the reliability related issues with regard to mechanical and electrical aspects are investigated. The BCB TSVs are fabricated using deep etching of annular trenches on a substrate, BCB cladding forming in the deep trenches, selective etching of the silicon posts in BCB claddings, and electroplating of copper plugs. The insulation capability and the configuration stability of BCB liners are evaluated by performing a thermal shock test and comparing the leakage currents before and after thermal shock. The results show that the BCB insulation capability does not change distinctly after thermal shock. Auger electronic spectroscopy (AES) is used to characterize copper diffusion through BCB thin films after high temperature treatment, and it is found that BCB is able to prevent copper diffusion at temperatures as high as 350 °C. Finite element analysis is performed to understand the thermal stress behaviors of BCB TSVs, and the simulation results show that BCB liners are able to reduce the thermal induced stresses in substrates, but increase the axial thermal expansion of copper plugs.

[1]  Characterization of reactive ion etching of benzocyclobutente in SF6/O2 plasmas , 2010 .

[2]  D. Henry,et al.  Polymer filling of medium density through silicon via for 3D-packaging , 2009, 2009 11th Electronics Packaging Technology Conference.

[3]  Cher Ming Tan,et al.  Electromigration performance of Through Silicon Via (TSV) - A modeling approach , 2010, Microelectron. Reliab..

[4]  Reza Ghodssi,et al.  Embedded benzocyclobutene in silicon: An integrated fabrication process for electrical and thermal isolation in MEMS , 2005 .

[5]  Edmund J. Sprogis,et al.  Wafer-level 3D integration technology , 2008, IBM J. Res. Dev..

[6]  L. Zhang,et al.  Achieving Stable Through-Silicon Via (TSV) Capacitance with Oxide Fixed Charge , 2011, IEEE Electron Device Letters.

[7]  S.-H. Hwang,et al.  Measurement of stresses in Cu and Si around through-silicon via by synchrotron X-ray microdiffraction for 3-dimensional integrated circuits , 2012, Microelectron. Reliab..

[8]  F. Huang,et al.  Thermal stability and degradation products analysis of benzocyclobutene-terminated imide polymers , 2005 .

[9]  M. Koyanagi,et al.  Three-Dimensional Integration Technology Based on Wafer Bonding With Vertical Buried Interconnections , 2006, IEEE Transactions on Electron Devices.

[10]  G. Q. Zhang,et al.  Analysis of Cu/low-k bond pad delamination by using a novel failure index , 2005, EuroSimE 2005. Proceedings of the 6th International Conference on Thermal, Mechanial and Multi-Physics Simulation and Experiments in Micro-Electronics and Micro-Systems, 2005..

[11]  Y.-L. Shen,et al.  Thermal expansion behavior of through-silicon-via structures in three-dimensional microelectronic packaging , 2012, Microelectron. Reliab..

[12]  D. Henry,et al.  Process solutions and polymer materials for 3D-WLP through silicon via filling , 2010, 2010 Proceedings 60th Electronic Components and Technology Conference (ECTC).

[13]  M. Koyanagi,et al.  Evaluation of Cu Diffusion From Cu Through-Silicon Via (TSV) in Three-Dimensional LSI by Transient Capacitance Measurement , 2011, IEEE Electron Device Letters.

[14]  S. Moreau,et al.  Reliability study of 3D-WLP through silicon via with innovative polymer filling integration , 2011, 2011 IEEE 61st Electronic Components and Technology Conference (ECTC).

[15]  Nonlinear thermal stress & strain analysis of through silicon vias with different structures and polymer filling , 2011, 2011 IEEE 13th Electronics Packaging Technology Conference.

[16]  M. E. Mills,et al.  Benzocyclobutene (DVS-BCB) polymer as an interlayer dielectric (ILD) material , 1997 .

[17]  Robert S. Patti,et al.  Three-Dimensional Integrated Circuits and the Future of System-on-Chip Designs , 2006, Proceedings of the IEEE.

[18]  Bart Vandevelde,et al.  Cu pumping in TSVs: Effect of pre-CMP thermal budget , 2011, Microelectron. Reliab..

[19]  Cheng-Ta Ko,et al.  Wafer-level bonding/stacking technology for 3D integration , 2010, Microelectron. Reliab..

[20]  Ingrid De Wolf,et al.  Processing assessment and adhesion evaluation of copper through-silicon vias (TSVs) for three-dimensional stacked-integrated circuit (3D-SIC) architectures , 2010, Microelectron. Reliab..

[21]  C. Zhang,et al.  Characterization and Design of Through-Silicon Via Arrays in Three-Dimensional ICs Based on Thermomechanical Modeling , 2011, IEEE Transactions on Electron Devices.

[22]  Suk-kyu Ryu,et al.  Thermo-mechanical reliability of 3-D ICs containing through silicon vias , 2009, 2009 59th Electronic Components and Technology Conference.

[23]  C. Selvanayagam,et al.  Modeling Stress in Silicon With TSVs and Its Effect on Mobility , 2011, IEEE Transactions on Components, Packaging and Manufacturing Technology.

[24]  Peter Ramm,et al.  3D System-on-Chip technologies for More than Moore systems , 2010, DTIP 2010.

[25]  G. Maier.  Low dielectric constant polymers for microelectronics , 2001 .

[26]  Jian-Qiang Lu,et al.  Thick benzocyclobutene etching using high density SF6/O2 plasmas , 2011 .

[27]  Jian-Qiang Lu,et al.  3-D Hyperintegration and Packaging Technologies for Micro-Nano Systems , 2009, Proceedings of the IEEE.

[28]  Suk-kyu Ryu,et al.  Thermal stress induced delamination of through silicon vias in 3-D interconnects , 2010, 2010 Proceedings 60th Electronic Components and Technology Conference (ECTC).

[29]  G. Lo,et al.  Influence of Bosch Etch Process on Electrical Isolation of TSV Structures , 2011, IEEE Transactions on Components, Packaging and Manufacturing Technology.

[30]  S. Thompson,et al.  Uniaxial-process-induced strained-Si: extending the CMOS roadmap , 2006, IEEE Transactions on Electron Devices.

[31]  Eric Beyne,et al.  Thermal stability of copper Through-Silicon Via barriers during IC processing , 2011, 2011 IEEE International Interconnect Technology Conference.

[32]  Suk-kyu Ryu,et al.  Impact of Near-Surface Thermal Stresses on Interfacial Reliability of Through-Silicon Vias for 3-D Interconnects , 2011, IEEE Transactions on Device and Materials Reliability.

[33]  C.K. Chen,et al.  A wafer-scale 3-D circuit integration technology , 2006, IEEE Transactions on Electron Devices.

[34]  V. Moroz,et al.  Performanace and reliability analysis of 3D-integration structures employing Through Silicon Via (TSV) , 2009, 2009 IEEE International Reliability Physics Symposium.

[35]  E. Beyne,et al.  Polymer Filling of Silicon Trenches for 3-D Through Silicon vias Applications , 2011, IEEE Transactions on Components, Packaging and Manufacturing Technology.

[36]  Katsuyuki Sakuma,et al.  Three-dimensional silicon integration , 2008, IBM J. Res. Dev..

[37]  E. Beyne,et al.  3-D Wafer-Level Packaging Die Stacking Using Spin-on-Dielectric Polymer Liner Through-Silicon Vias , 2011, IEEE Transactions on Components, Packaging and Manufacturing Technology.

[38]  Zheyao Wang,et al.  Benzocyclobutene polymer filling of high aspect-ratio annular trenches for fabrication of Through-Silicon-Vias (TSVs) , 2012, Microelectron. Reliab..

[39]  S. W. Ho,et al.  3D interconnection process development and integration with low stress TSV , 2010, 2010 Proceedings 60th Electronic Components and Technology Conference (ECTC).

[40]  John H. Lau,et al.  Effects of etch rate on scallop of through-silicon vias (TSVs) in 200mm and 300mm wafers , 2011, 2011 IEEE 61st Electronic Components and Technology Conference (ECTC).