A practical approach to crosstalk noise verification of static CMOS designs

In deep submicron technologies, coupling capacitance significantly dominates the total parasitic capacitance. This causes crosstalk noise to be induced on quiescent signals which could lead to catastrophic failures. This paper provides an overview of the issues related to crosstalk noise in static CMOS designs and presents a practical approach to full-chip crosstalk noise verification. A grouping based method is described for identification of potential victims and associated aggressors, in the absence of timing information. Results from crosstalk verification of a large DSP design is presented.

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