A hardware detector for image LSB built-in hiding information

The invention discloses a hardware detector aiming to insert hidden information into an LSB image, which comprises an address generator, a memory, and a detection engine. Wherein, the address generator connects with the memory through an address bus of 22 bits, and the memory connects with the detection engine through a data bus of 32 bits. The detector maps the RS hidden detection algorithm to hardware to be realized, which adopts a 3-level pipeline structure, thus improves data processing efficiency; the width of the data bus of the detector is 32 bits, which possesses a strong parallel processing capability and can parallel process 4 image pixels of 8 bits at the same time; the value of image pixels is saved in the memory, and the data saved in the memory is output to the detector through a memory address generated by the address generator which supports 2 scanning modes. The invention has a very strong data processing capability and the data processing speed is much higher than the current program realized by software.