Processor: A 64-Core SoC with Mesh Interconnect
暂无分享,去创建一个
David Wentzlaff | Matthew Mattina | Liewei Bao | Bruce Edwards | Chyi-Chang Miao | Carl Ramey | John F. Brown | John MacKay | John Amann | Walker Anderson | Jon C. Zook | Shane Bell | Rich Conlin | Kevin Joyce | Vince Leung | Mike Reif | Ethan Berger | Nat Fairbanks | Durlov Khan | Froilan Montenegro | Jay Stickney | John Zook | D. Wentzlaff | Matthew Mattina | Liewei Bao | Bruce Edwards | Carl Ramey | Chyi-Chang Miao | J. Amann | W. Anderson | E.‐M. Berger | John F. Brown | Shane L. Bell | R. Conlin | Kevin Joyce | Vincent Leung | J. MacKay | M. Reif | N. Fairbanks | Durlov Khan | Froilan Montenegro | J. Stickney
[1] Ashok Kumar,et al. An 8-Core 64-Thread 64b Power-Efficient SPARC SoC , 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.
[2] Saurabh Dighe,et al. An 80-Tile 1.28TFLOPS Network-on-Chip in 65nm CMOS , 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.
[3] V. Strumpen,et al. A 16-issue multiple-program-counter microprocessor with point-to-point scalar operand network , 2003, 2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC..
[4] Gaurav Mittal,et al. Design of the Power6 Microprocessor , 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.
[5] R. Kumar,et al. An Integrated Quad-Core Opteron Processor , 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.