Load Sharing Replicated Buffered Banyan Networks With Priority Traffic

In this paper we investigate further the performance of a fault tolerant load sharing replicated buffered banyan network switch design. We look at the effect increasing the Switch Element (SE) degree has on the performance of the system and propose a simple modification to the system to transmit priority traffic. These results highlight the excellent performance and flexibility that these load sharing replication buffered banyan networks provide.

[1]  Hiroshi Kuwahara,et al.  A shared buffer memory switch for an ATM exchange , 1989, IEEE International Conference on Communications, World Prosperity Through Communications,.

[2]  Seong Leong Ng,et al.  A fault tolerant load sharing replicated buffered banyan network , 1995, Proceedings 1st International Conference on Algorithms and Architectures for Parallel Processing.

[3]  Marc Snir,et al.  The Performance of Multistage Interconnection Networks for Multiprocessors , 1983, IEEE Transactions on Computers.

[4]  Jonathan S. Turner,et al.  Improved queueing analysis of shared buffer switching networks , 1993, TNET.

[5]  Masayuki Murata,et al.  Survey of switching techniques in high-speed networks and their performance , 1990, Proceedings. IEEE INFOCOM '90: Ninth Annual Joint Conference of the IEEE Computer and Communications Societies@m_The Multiple Facets of Integration.

[6]  Manoj Kumar,et al.  Performance of Unbuffered Shuffle-Exchange Networks , 1986, IEEE Transactions on Computers.

[7]  Ted H. Szymanski,et al.  Markov chain analysis of packet-switched banyans with arbitrary switch sizes, queue sizes, link multiplicities and speedups , 1989, IEEE INFOCOM '89, Proceedings of the Eighth Annual Joint Conference of the IEEE Computer and Communications Societies.

[8]  Jonathan S. Turner,et al.  Design of a broadcast packet switching network , 1988, IEEE Trans. Commun..

[9]  Bill Dewar,et al.  On improving the performance of shared buffered banyan networks , 1995, Proceedings IEEE International Conference on Communications ICC '95.

[10]  Robert J. McMillen,et al.  The Multistage Cube: A Versatile Interconnection Network , 1981, Computer.

[11]  Shoichi Shimizu,et al.  A One-Chip Scalable 8 * 8 ATM Switch LSI Employing Shared Buffer Architecture , 1991, IEEE J. Sel. Areas Commun..