A trace-based binary compilation framework for energy-aware computing

Energy-aware compilers are becoming increasingly important for embedded systems due to the need to meet conflicting constraints on time, code size and power consumption. We introduce a trace-based, offline compiler framework on binaries and demonstrate its benefits in supporting energy optimisations. The key innovation lies in identifying frequently executed paths in a binary program and duplicating them as single-entry traces. Separating frequently from infrequently executed paths enables the compiler to focus both performance and energy optimisations on the hot traces.Traces constructed at the level of binaries are inherently inter-procedural, spanning both application and library code. Such a framework allows an embedded application developer to exploit optimisation opportunities made possible due to the information that is available only at link time.We describe the implementation of our trace-based framework in alto, a link-time optimiser for the Alpha architecture. We present a new algorithm for constructing the hot traces from binaries. This algorithm is both effective (since the execution cycles are mostly spent on traces) and practical (due to small code size increases caused). We have developed and implemented a new optimisation to reduce the functional unit leakage energy. We show how the traces facilitate the development of such an optimisation, which results in significant leakage energy savings for benchmark programs at the cost of small performance penalties.

[1]  Richard Johnson,et al.  The Transmeta Code Morphing#8482; Software: using speculation, recovery, and adaptive retranslation to address real-life challenges , 2003, CGO.

[2]  Yunheung Paek,et al.  Finding effective optimization phase sequences , 2003, LCTES '03.

[3]  Catherine H. Gebotys Low energy memory and register allocation using network flow , 1997, DAC.

[4]  Mahmut T. Kandemir,et al.  EAC: a compiler framework for high-level energy estimation and optimization , 2002, Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition.

[5]  Gurindar S. Sohi,et al.  A static power model for architects , 2000, MICRO 33.

[6]  Scott A. Mahlke,et al.  Effective compiler support for predicated execution using the hyperblock , 1992, MICRO 25.

[7]  Shekhar Y. Borkar,et al.  Design challenges of technology scaling , 1999, IEEE Micro.

[8]  Björn Lisper,et al.  Data caches in multitasking hard real-time systems , 2003, RTSS 2003. 24th IEEE Real-Time Systems Symposium, 2003.

[9]  Mahmut T. Kandemir,et al.  Influence of compiler optimizations on system power , 2000, Proceedings 37th Design Automation Conference.

[10]  Lars Wehmeyer,et al.  Energy aware compilation for DSPs with SIMD instructions , 2002, LCTES/SCOPES '02.

[11]  Saumya K. Debray,et al.  Alto: a platform for object code modification , 1999 .

[12]  Joseph A. Fisher,et al.  Trace Scheduling: A Technique for Global Microcode Compaction , 1981, IEEE Transactions on Computers.

[13]  Santosh Pande,et al.  Optimizing Static Power Dissipation by Functional Units in Superscalar Processors , 2002, CC.

[14]  Brad Calder,et al.  Value profiling , 1997, Proceedings of 30th Annual International Symposium on Microarchitecture.

[15]  Sharad Malik,et al.  Compile-time dynamic voltage scaling settings: opportunities and limits , 2003, PLDI '03.

[16]  Mary Lou Soffa,et al.  Predicting the impact of optimizations for embedded systems , 2003, LCTES '03.

[17]  Cristina Cifuentes,et al.  Machine-adaptable dynamic binary translation , 2000, Dynamo.

[18]  Wei Zhang,et al.  A compiler approach for reducing data cache energy , 2003, ICS '03.

[19]  Peter Marwedel,et al.  Analysis of the influence of register file size on energyconsumption, code size, and execution time , 2001, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[20]  Mahmut T. Kandemir,et al.  Energy-conscious compilation based on voltage scaling , 2002, LCTES/SCOPES '02.

[21]  Mahmut T. Kandemir,et al.  Adapting instruction level parallelism for optimizing leakage in VLIW architectures , 2003, LCTES.

[22]  Jenq Kuen Lee,et al.  Compiler optimization on instruction scheduling for low power , 2000, ISSS '00.

[23]  Richard Johnson,et al.  The Transmeta Code Morphing/spl trade/ Software: using speculation, recovery, and adaptive retranslation to address real-life challenges , 2003, International Symposium on Code Generation and Optimization, 2003. CGO 2003..

[24]  William J. Bowhill,et al.  Design of High-Performance Microprocessor Circuits , 2001 .