An Ultra-high Speed Public Key Encryption Processor

This paper describes the architecture and design of a public key encryption processor which implements the RSA algorithm with key lengths of512 bits. The chip, which is 6.2 by 4.2 millimetres, has been designed in a 0.7 micron CMOS, silicon on insulator process and has a target clock speed of 15OMHz. It is a self contained subsystem which interfaces directly to standard microprocessors and will be capable of encrypting at rates well in excess of 64k baud (for contractural reasons we are unable, at this time, to disclose the emct speed of operation).

[1]  John Oldfield,et al.  A Single Chip Public Key Encryption Sub-System , 1988, ESSCIRC '88: Fourteenth European Solid-State Circuits Conference.

[2]  J. Colinge.  Silicon-on-Insulator Technology: Materials to VLSI , 1991 .

[3]  Adi Shamir,et al.  A method for obtaining digital signatures and public-key cryptosystems , 1978, CACM.

[4]  J. Colinge.  Silicon-on-Insulator Technology , 1991 .

[5]  J. M. Stern,et al.  Silicon-on-insulator (SOI): A High Performance ASIC Technology , 1992, 1992 Proceedings of the IEEE Custom Integrated Circuits Conference.

[6]  Whitfield Diffie,et al.  New Directions in Cryptography , 1976, IEEE Trans. Inf. Theory.