An efficient all-digital IR-Drop Alarmer for DVFS-based SoC

For 40nm and below technologies, billions of transistors can be integrated into a single chip. Meanwhile, the operation frequency has reached over Giga Hertz. In this case, highly synchronized switching activities can induce significant current, which leads to IR-drop. Excessive IR-drop can cause timing failure, abnormal reset, or disruption of data processing. As a result, dynamic voltage and frequency scaling (DVFS) system implemented effective adaptation strategies are widely used by SoCs to mitigate IR-Drop noise and stabilize performance. As the basis of DVFS action, economic and accurate IR-drop monitors are in great need. This paper presents a novel and efficient IR-Drop Alarmer, which can cooperate with the DVFS system for fast IR-drop adaptation. The IR-drop alarming threshold of the proposed sensor is configurable between 45mV to 120mV. Considering a 1.1ns width IR-drop noise, the IR noise sampling window can be as small as 0.125ns, with alarming duration error rate less than 6.8% for 97% of the Monte Carlo samples considering process variations. Furthermore, the proposed alarmer is composed by all-digital standard gates without an y high frequency sampling clock, which is of low area overhead and power consumption.

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