6 Efficient Technology Mapping Method for PAL-Based Devices

The core of a contemporary CPLD device is a PAL-based logic block which consists of a programmable AND matrix and a fixed OR matrix. A new technology mapping method for PAL-based devices based on the analysis of graph of outputs is described. The presented approach uses original method for illustrating a minimized form of a multi-output Boolean function. Graph node represents groups of multiple-output implicants with common output part. The essence of the method is the process of searching for appropriate multi-output implicants that can be shared by several functions. A new method for the description of cascaded feedback connections is presented. The experimental results show that the proposed algorithm leads to significant reduction of chip area used by resulting circuits.

[1]  David Harrison,et al.  A fast partitioning method for PLA-based FPGAs , 1992, IEEE Design & Test of Computers.

[2]  Martin Bolton.  Digital systems design with programmable logic , 1990, Electronic systems engineering series.

[3]  Tsutomu Sasao.  Application of multiple-valued logic to a serial decomposition of PLAs , 1989, Proceedings. The Nineteenth International Symposium on Multiple-Valued Logic.

[4]  F. Wolf,et al.  Efficient decomposition of assigned sequential machines and Boolean functions for PLD implementations , 1995, Proceedings Electronic Technology Directions to the Year 2000.

[5]  A.R. Newton,et al.  Boolean decomposition of programmable logic arrays , 1988, Proceedings of the IEEE 1988 Custom Integrated Circuits Conference.

[6]  Jason Helge Anderson,et al.  Technology mapping for large complex PLDs , 1998, Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175).

[7]  Seiyang Yang,et al.  Optimum and suboptimum algorithms for input encoding and its relationship to logic minimization , 1991, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[8]  D. Kania.  Efficient approach to synthesis of multioutput Boolean functions on PAL-based devices , 2003 .

[9]  Alberto L. Sangiovanni-Vincentelli,et al.  Boolean decomposition in multi-level logic optimization , 1988, [1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers.

[10]  Seiyang Yang,et al.  PLA decomposition with generalized decoders , 1989, 1989 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

[11]  Srinivas Devadas,et al.  Exact algorithms for output encoding, state assignment, and four-level Boolean minimization , 1991, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[12]  Dariusz Kania.  A technology mapping algorithm for PAL-based devices using multi-output function graphs , 2000, Proceedings of the 26th Euromicro Conference. EUROMICRO 2000. Informatics: Inventing the Future.

[13]  Seiyang Yang,et al.  PLADE: a two-stage PLA decomposition , 1992, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[14]  D. Kania.  Two-level logic synthesis on PALs , 1999 .

[15]  L. Jozwiak,et al.  An efficient method for decomposition of multiple-output Boolean functions and assigned sequential machines , 1992, [1992] Proceedings The European Conference on Design Automation.

[16]  TingTing Hwang,et al.  A technology mapping algorithm for CPLD architectures , 2002, 2002 IEEE International Conference on Field-Programmable Technology, 2002. (FPT). Proceedings..

[17]  Hana Kubatova,et al.  Flexible Two-Level Boolean Minimizer BOOM-II and Its Applications , 2006, 9th EUROMICRO Conference on Digital System Design (DSD'06).

[18]  Giovanni De Micheli,et al.  Synthesis and Optimization of Digital Circuits , 1994 .

[19]  Robert K. Brayton,et al.  Three-level decomposition with application to PLDs , 1991, [1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors.

[20]  P. Ashar,et al.  Sequential Logic Synthesis , 1991 .

[21]  Alexander Saldanha,et al.  PLA optimization using output encoding , 1988, [1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers.

[22]  Chuan-Jin Shi,et al.  An efficient algorithm for constrained encoding and its applications , 1993, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[23]  Jan Hlavicka,et al.  BOOM-a heuristic Boolean minimizer , 2001, IEEE/ACM International Conference on Computer Aided Design. ICCAD 2001. IEEE/ACM Digest of Technical Papers (Cat. No.01CH37281).

[24]  A E A Almaini,et al.  Optimisation of Reed-Muller PLA implementations , 2002 .