Formal reasoning with Verilog HDL

Most hardware verification techniques tend to fall under one of two broad, yet separate caps: simulation or formal verification. This paper briefly presents a framework in which formal verification plays a crucial role within the standard approach currently used by the hardware industry. As a basis for this, the formal semantics of Verilog HDL are defined, and properties about synchronization and mutual exclusion algorithms are proved.

[1]  Egon Brger,et al.  Formal de nition of an abstract VHDL''''93 simulator by EA - machines , 1995 .

[2]  Zhou Chaochen,et al.  Duration Calculi: An overview , 1993 .

[3]  Carlos Delgado Kloos,et al.  Formal Semantics for VHDL , 1995 .

[4]  Carlos Delgado Kloos,et al.  Clean formal semantics for VHDL , 1994, Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC.

[5]  Michael J. C. Gordon,et al.  The semantic challenge of Verilog HDL , 1995, Proceedings of Tenth Annual IEEE Symposium on Logic in Computer Science.

[6]  Qiwen Xu,et al.  Semantics and Verifikation of Extended Phase Transition Systems in Duration Calculus , 1997, HART.

[7]  John Van Tassel.  A Formalisation of the VHDL Simulation Cycle , 1992, TPHOLs.

[8]  Michael R. Hansen,et al.  Chopping a point , 1996 .

[9]  Karen C. Davis.  A Denotational Definition of the VHDL Simulation Kernel , 1993, CHDL.

[10]  C. A. R. Hoare,et al.  A Calculus of Durations , 1991, Inf. Process. Lett..