FlexSoC: Combining Flexibility and Efficiency in SoC Designs

The FlexSoC project aims at developing a design framework that makes it possible to combine the computational speed and energy-efficiency of specialized hardware accelerators with the flexibility of programmable processors. FlexSoC approaches this problem by defining a uniform programming interface across the heterogeneous structure of processing resources. This paper justifies our approach and also discusses the central research issues we will focus on in the areas of VLSI design, computer architecture, and programming and verification.

[1]  Mary Sheeran,et al.  The Design and Verification of a Sorter Core , 2001, CHARME.

[2]  Amir Roth,et al.  DISE: a programmable macro engine for customizing applications , 2003, ISCA '03.

[3]  Mary Sheeran,et al.  Lava: hardware design in Haskell , 1998, ICFP '98.

[4]  Paul Hudak,et al.  Modular domain specific languages and tools , 1998, Proceedings. Fifth International Conference on Software Reuse (Cat. No.98TB100203).

[5]  Jianwei Chen,et al.  SimWattch: An Approach to Integrate Complete-System with User-Level Performance/Power Simulators , 2003 .

[6]  P. Larsson-Edefors,et al.  A deep submicron power estimation methodology adaptable to variations between power characterization and estimation , 2003, Proceedings of the ASP-DAC Asia and South Pacific Design Automation Conference, 2003..

[7]  Oege de Moor,et al.  Compiling embedded languages , 2003, J. Funct. Program..

[8]  Margaret Martonosi,et al.  Augmenting Modern Superscalar Architectures with Configurable Extended Instructions , 2000, IPDPS Workshops.

[9]  Robert Wilson,et al.  Compiling Java just in time , 1997, IEEE Micro.

[10]  Narayanan Vijaykrishnan,et al.  Java Runtime Systems: Characterization and Architectural Implications , 2001, IEEE Trans. Computers.

[11]  Kunle Olukotun,et al.  A Single-Chip Multiprocessor , 1997, Computer.

[12]  Trevor N. Mudge,et al.  Reducing code size with run-time decompression , 2000, Proceedings Sixth International Symposium on High-Performance Computer Architecture. HPCA-6 (Cat. No.PR00550).

[13]  Miodrag Potkonjak,et al.  MediaBench: a tool for evaluating and synthesizing multimedia and communications systems , 1997, Proceedings of 30th Annual International Symposium on Microarchitecture.

[14]  Bjorn De Sutter,et al.  Compiler techniques for code compaction , 2000, TOPL.

[15]  Amir Roth,et al.  A DISE implementation of dynamic code decompression , 2003, LCTES.