Routing Pressure: A Channel-Related and Traffic-Aware Metric of Routing Algorithm
暂无分享,去创建一个
[1] W. Dally,et al. Route packets, not wires: on-chip interconnection networks , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).
[2] Minghua Tang,et al. A new method of designing NoC routing algorithm , 2012, 2012 2nd International Conference on Consumer Electronics, Communications and Networks (CECNet).
[3] Radu Marculescu,et al. A traffic-aware adaptive routing algorithm on a highly reconfigurable network-on-chip architecture , 2012, CODES+ISSS.
[4] Natalie D. Enright Jerger,et al. DBAR: An efficient routing algorithm to support multiple concurrent applications in networks-on-chip , 2011, 2011 38th Annual International Symposium on Computer Architecture (ISCA).
[5] Jie Wu,et al. A Fault-Tolerant and Deadlock-Free Routing Protocol in 2D Meshes Based on Odd-Even Turn Model , 2003, IEEE Trans. Computers.
[6] Xiaola Lin,et al. Network-on-Chip Routing Algorithms by Breaking Cycles , 2010, ICA3PP.
[7] Radu Marculescu,et al. Exploiting Emergence in On-Chip Interconnects , 2014, IEEE Transactions on Computers.
[8] Ge-Ming Chiu,et al. The Odd-Even Turn Model for Adaptive Routing , 2000, IEEE Trans. Parallel Distributed Syst..
[9] José Duato,et al. Segment-based routing: an efficient fault-tolerant routing algorithm for meshes and tori , 2006, Proceedings 20th IEEE International Parallel & Distributed Processing Symposium.
[10] Ming Li,et al. DyXY - a proximity congestion-aware deadlock-free dynamic routing method for network on chip , 2006, 2006 43rd ACM/IEEE Design Automation Conference.
[11] Radu Marculescu,et al. On-chip traffic modeling and synthesis for MPEG-2 video applications , 2004, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[12] William J. Dally,et al. Principles and Practices of Interconnection Networks , 2004 .
[13] Vincenzo Catania,et al. Application Specific Routing Algorithms for Networks on Chip , 2009, IEEE Transactions on Parallel and Distributed Systems.
[14] Luca Benini,et al. Networks on Chips : A New SoC Paradigm , 2022 .
[15] Radu Marculescu,et al. Non-Stationary Traffic Analysis and Its Implications on Multicore Platform Design , 2011, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[16] Huawei Li,et al. An abacus turn model for time/space-efficient reconfigurable routing , 2011, 2011 38th Annual International Symposium on Computer Architecture (ISCA).
[17] Radu Marculescu,et al. Statistical physics approaches for network-on-chip traffic characterization , 2009, CODES+ISSS '09.
[18] Hannu Tenhunen,et al. A generic adaptive path-based routing method for MPSoCs , 2011, J. Syst. Archit..
[19] Loren Schwiebert,et al. Optimal Fully Adaptive Minimal Wormhole Routing for Meshes , 1995, J. Parallel Distributed Comput..
[20] Radu Marculescu,et al. Quantum-Like Effects in Network-on-Chip Buffers Behavior , 2007, 2007 44th ACM/IEEE Design Automation Conference.
[21] Mohamed Bakhouya,et al. A buffer-space allocation approach for application-specific Network-on-Chip , 2011, 2011 9th IEEE/ACS International Conference on Computer Systems and Applications (AICCSA).
[22] Akif Ali,et al. Near-optimal worst-case throughput routing for two-dimensional mesh networks , 2005, 32nd International Symposium on Computer Architecture (ISCA'05).
[23] Antoine Fraboulet,et al. Long-range dependence and on-chip processor traffic , 2009, Microprocess. Microsystems.
[24] Stephen W. Keckler,et al. Regional congestion awareness for load balance in networks-on-chip , 2008, 2008 IEEE 14th International Symposium on High Performance Computer Architecture.