A 0.13/spl mu/m CMOS EDGE/UMTS/WLAN Tri-Mode /spl Delta//spl Sigma/ ADC with -92dB THD

A 2-2 cascaded multi-standard DeltaSigma modulator achieves a OR of 88/79/67dB in EDGE/UMTS/WLAN mode, respectively. With a high linearity of -92dB THD and 34dBm IIP3 for EDGE, this ADC is suitable for wireless applications. Implemented in 0.13 mum CMOS and occupying 0.4mm2, the modulator covers 0.1-to-10MHz signal bandwidth with scalable power consumption between 2.9 and 20.5mW from a 1.2V supply.

[1]  R. Reutemann,et al.  A 50mW HSDPA Baseband Receiver ASIC with Multimode Digital Front-End , 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[2]  R. V. Veldhoven A triple-mode continuous-time ΣΔ modulator with switched-capacitor feedback DAC for a GSM-EDGE/CDMA2000/UMTS receiver , 2003, IEEE J. Solid State Circuits.

[3]  O. Oliaei,et al.  A 5-mW sigma-delta modulator with 84-dB dynamic range for GSM/EDGE , 2002 .

[4]  T. Burger,et al.  A 13.5mW, 185 MSample/s /spl Delta//spl Sigma/-modulator for UMTS/GSM dual-standard IF reception , 2001, 2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177).