Testing compilers for programmable switches through switch hardware simulation

Programmable switches have emerged as powerful and flexible alternatives to fixed-function forwarding devices. But because of the unique hardware constraints of network switches, the design and implementation of compilers targeting these devices is tedious and error-prone. Despite the important role that compilers play in software development, there is a dearth of tools for testing compilers for programmable network devices. We present Druzhba, a programmable switch simulator used for testing compilers targeting programmable packet-processing substrates. We show that we can model the low-level behavior of a switch's programmable hardware. We further show how compiler developers can target Druzhba as a compiler backend. Generated machine code programs are fed into Druzhba and tested using a fuzzing-based approach that allows compiler developers to test the correctness of their compilers. Using a program-synthesis-based compiler as a case study, we demonstrate how Druzhba has been successful in testing compiler-generated machine code for our simulated switch pipeline instruction set.

[1]  Zhendong Su,et al.  Skeletal program enumeration for rigorous compiler testing , 2016, PLDI.

[2]  Haoyu Song,et al.  Protocol-oblivious forwarding: unleash the power of SDN through a future-proof forwarding plane , 2013, HotSDN '13.

[3]  Nick McKeown,et al.  OpenFlow: enabling innovation in campus networks , 2008, CCRV.

[4]  Vladimir Braverman,et al.  NetLock: Fast, Centralized Lock Management Using Programmable Switches , 2020, SIGCOMM.

[5]  George Varghese,et al.  Forwarding metamorphosis: fast programmable match-action processing in hardware for SDN , 2013, SIGCOMM.

[6]  Kang G. Shin,et al.  The BLUE active queue management algorithms , 2002, TNET.

[7]  Jun Bi,et al.  NS4: Enabling Programmable Data Plane Simulation , 2018, SOSR.

[8]  Hongyu Zhang,et al.  Learning to Prioritize Test Programs for Compiler Testing , 2017, 2017 IEEE/ACM 39th International Conference on Software Engineering (ICSE).

[9]  C. Cordell Green,et al.  What Is Program Synthesis? , 1985, J. Autom. Reason..

[10]  David Walker,et al.  SNAP: Stateful Network-Wide Abstractions for Packet Processing , 2015, SIGCOMM.

[11]  Jiang Zhu,et al.  Making Large Scale Deployment of RCP Practical for Real Networks , 2008, IEEE INFOCOM 2008 - The 27th Conference on Computer Communications.

[12]  Keith D. Cooper,et al.  Engineering a Compiler , 2003 .

[13]  Nick McKeown,et al.  p4v: practical verification for programmable data planes , 2018, SIGCOMM.

[14]  Sumit Gulwani,et al.  Program Synthesis , 2017, Software Systems Safety.

[15]  Jitendra Padhye,et al.  CrystalNet: Faithfully Emulating Large Production Networks , 2017, SOSP.

[16]  Peter M. Athanas,et al.  p4pktgen: Automated Test Case Generation for P4 Programs , 2018, SOSR.

[17]  Srikanth Kandula,et al.  Harnessing TCPs Burstiness using Flowlet Switching , 2004 .

[18]  Xuejun Yang,et al.  Finding and understanding bugs in C compilers , 2011, PLDI '11.

[19]  Hang Zhu,et al.  Multitenancy for Fast and Programmable Networks in the Cloud , 2020, HotCloud.

[20]  Ariel Orda,et al.  dRMT: Disaggregated Programmable Switching , 2017, SIGCOMM.

[21]  Nick Feamster,et al.  The road to SDN: an intellectual history of programmable networks , 2014, CCRV.

[22]  Alvin Cheung,et al.  Packet Transactions: High-Level Programming for Line-Rate Switches , 2015, SIGCOMM.

[23]  Samar Abdi,et al.  PFPSim: A programmable forwarding plane simulator , 2016, 2016 ACM/IEEE Symposium on Architectures for Networking and Communications Systems (ANCS).

[24]  Arvind Krishnamurthy,et al.  Gallium: Automated Software Middlebox Offloading to Programmable Switches , 2020, SIGCOMM.

[25]  Anirudh Sivaraman,et al.  Switch Code Generation Using Program Synthesis , 2020, SIGCOMM.

[26]  Taegyun Kim,et al.  Autogenerating Fast Packet-Processing Code Using Program Synthesis , 2019, HotNets.

[27]  George Varghese,et al.  CONGA: distributed congestion-aware load balancing for datacenters , 2015, SIGCOMM.

[28]  Minlan Yu,et al.  Lyra: A Cross-Platform Language and Compiler for Data Plane Programming on Heterogeneous ASICs , 2020, SIGCOMM.

[29]  Anirudh Sivaraman,et al.  Language-Directed Hardware Design for Network Performance Monitoring , 2017, SIGCOMM.