Designing a Fast and Reliable Main Memory with Memristor Technology

Several memory vendors are pursuing different kinds of memory cells that can offer high density, non-volatility, high performance, and high endurance. In this work, we focus on Memristor technology and identify some of the significant problems in state-of-the-art implementations. These problems include sneak currents during reads and non-uniformity in cell behavior within an array. These problems manifest as long read latencies, long write latencies, and high cache line error rates. To address these problems, we introduce multiple innovations to a memristor memory system: (i) We employ a background sneak current read that can be amortized across several other data reads from the same column, thus introducing “open-column” semantics for memristor array access. (ii) We also introduce a novel data mapping policy that reduces multi-bit error rates in cache lines. However, this policy also increases the average write latency for a cache line. (iii) We overcome this drawback by introducing data compression and avoiding poorly behaving cells during writes. The result is a memristor memory system that performs 12% better and has 30X lower probability of suffering a two-bit error compared to the baseline.