Stacked devices for SEU immune design

A stacked transistor on SOI shows the potential to provide soft error upset immune designs. Key design elements are presented and analyzed showing tradeoffs between standard SOI devices and stacked devices, as well as alternative layouts to optimize soft error upset immunity.

[1]  V. Zyuban,et al.  POWER7TM local clocking and clocked storage elements , 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).

[2]  K. Bernstein,et al.  Soft error rate scaling for emerging SOI technology options , 2002, 2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303).

[3]  P. Oldiges,et al.  Technologies to further reduce soft error susceptibility in SOI , 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

[4]  A. Kumar,et al.  SOI series MOSFET for embedded high voltage applications and soft-error immunity , 2008, 2008 IEEE International SOI Conference.

[5]  Subramanian S. Iyer,et al.  45-nm silicon-on-insulator CMOS technology integrating embedded DRAM for high-performance server and ASIC applications , 2011, IBM J. Res. Dev..

[6]  J. Laskar,et al.  A Novel Multi-Stack Device Structure and its Analysis for High Power CMOS Switch Design , 2007, 2007 IEEE/MTT-S International Microwave Symposium.