The parallel complexity of minimizing column conflicts

Two-layer channel routers typically require a post-processing phase to reduce or eliminate column conflicts. Attempts have been made to parallelize this problem using local search heuristics that swap horizontal channel wire segments. The authors show that all such heuristics for this problem are P-hard and unlikely to be efficiently parallelizable.<<ETX>>

[1]  Daniel R. Greening,et al.  Parallel simulated annealing techniques , 1990 .

[2]  C. D. Gelatt,et al.  Optimization by Simulated Annealing , 1983, Science.

[3]  R. Ladner The circuit value problem is log space complete for P , 1975, SIGA.

[4]  David N. Deutsch A “DOGLEG” channel router , 1976, DAC 1976.

[5]  Markus G. Wloka Parallel VLSI Synthesis , 1991 .

[6]  Prithviraj Banerjee,et al.  Parallel Simulated Annealing Algorithms for Cell Placement on Hypercube Multiprocessors , 1990, IEEE Trans. Parallel Distributed Syst..

[7]  Thomas G. Szymanski Dogleg Channel Routing is NP-Complete , 1985, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[8]  Majid Sarrafzadeh Channel-Routing Problem in the Knock-Knee Mode Is NP-Complete , 1987, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[9]  Brian W. Kernighan,et al.  An efficient heuristic procedure for partitioning graphs , 1970, Bell Syst. Tech. J..

[10]  John E. Savage,et al.  On Parallelizing Graph-Partitioning Heuristics , 1990, ICALP.

[11]  R. M. Mattheyses,et al.  A Linear-Time Heuristic for Improving Network Partitions , 1982, 19th Design Automation Conference.

[12]  Ronald L. Rivest,et al.  A "Greedy" Channel Router , 1982, DAC 1982.

[13]  Takeshi Yoshimura,et al.  Efficient Algorithms for Channel Routing , 1982, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[14]  Alan Siegel,et al.  Optimal wiring between rectangles , 1981, STOC '81.

[15]  Alberto L. Sangiovanni-Vincentelli,et al.  A New Symbolic Channel Router: YACR2 , 1985, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[16]  Markus G. Wloka,et al.  Parallel Graph-Embedding and the Mob Heuristic , 1991 .

[17]  N. Metropolis,et al.  Equation of State Calculations by Fast Computing Machines , 1953, Resonance.

[18]  L. Goldschlager The monotone and planar circuit value problems are log space complete for P , 1977, SIGA.

[19]  John E. Savage,et al.  Parallelism in Graph-Partitioning , 1991, J. Parallel Distributed Comput..

[20]  Akihiro Hashimoto,et al.  Wire routing by optimizing channel assignment within large apertures , 1971, DAC.

[21]  Mihalis Yannakakis,et al.  Simple Local Search Problems That are Hard to Solve , 1991, SIAM J. Comput..