Power Aware High Level Synthesis of Hardware Coprocessors

Power reduction techniques such as clock-gating are used in almost all the ASIC designs. This technique helps in achieving quite a lot of power savings. Logic synthesis tools provide a good support for the implementation of clock-gating. However, above RTL there are not many existing techniques/tools. This paper presents detailed analysis of enabling clock-gating around high-level synthesis. We propose a novel system-level design methodology, which utilizes a 'relative power reduction model' that can help in predicting the impact of clock-gating on each register/bank quickly and accurately, by simulating the design at a cycle accurate transaction-level. As a result, our approach can automatically find the appropriate registers to clock-gate, guided by the system-level simulation. We also show how clock-gating can be enabled from the C source code providing flexibility to a designer to perform power-aware design trade-offs from high-level description.