A CMOS D-band low noise amplifier with 22.4dB gain and a 3dB bandwidth of 16GHz for wireless chip to chip communication

This paper presents a D-band six-stage low noise amplifier design in 65nm CMOS process. The single stage amplifier consists of combined cascode topology and common source topology to achieve high gain and save power consumption. For a high-data rate communication system, the wideband characteristic is very important. In order to enhance the 3 dB bandwidth, a two-center frequency technique and inductive feedback technique are used. The odd and even stages are designed to operate at 115 GHz and 125 GHz, respectively. In addition, the amplifier was realized by a conjugate matching technique to achieve low-loss between each stage. The measured results show that the low noise amplifier can provide a gain of 22.4dB with a 3dB bandwidth of 16GHz. The measured OP1dB is −4.5 dBm at 120 GHz. The minimum noise figure was 11.4dB at 117 GHz. The core chip size is 980 × 200 m2 and the power consumption of the proposed low noise amplifier is 61mW at a supply voltage of 1.7V. To the authors' knowledge, this is the best performance (gain −3dB bandwidth product) with low power consumption in 65nm CMOS at D-band frequency.

[1]  Corrado Carta,et al.  A 1.1V 150GHz amplifier with 8dB gain and +6dBm saturated output power in standard digital 65nm CMOS using dummy-prefilled microstrip lines , 2009, 2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

[2]  Qun Jane Gu,et al.  A Three Stage, Fully Differential 128–157 GHz CMOS Amplifier with Wide Band Matching , 2011, IEEE Microwave and Wireless Components Letters.

[3]  Ali M. Niknejad,et al.  Low-Power mm-Wave Components up to 104GHz in 90nm CMOS , 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[4]  Chien-Nan Kuo,et al.  A 147 GHz fully differential D-band amplifier design in 65 nm CMOS , 2013, 2013 Asia-Pacific Microwave Conference Proceedings (APMC).

[5]  Hiroyuki Ito,et al.  A simple through-only de-embedding method for on-wafer S-parameter measurements up to 110 GHz , 2008, IMS 2008.

[6]  Chul Woo Byeon,et al.  A 67-mW 10.7-Gb/s 60-GHz OOK CMOS Transceiver for Short-Range Wireless Communications , 2013, IEEE Transactions on Microwave Theory and Techniques.

[7]  Guo-Wei Huang,et al.  60GHz high-gain low-noise amplifiers with a common-gate inductive feedback in 65nm CMOS , 2011, 2011 IEEE Radio Frequency Integrated Circuits Symposium.

[8]  Jae Jin Lee,et al.  60-GHz Gigabits-Per-Second OOK Modulator With High Output Power in 90-nm CMOS , 2011, IEEE Transactions on Circuits and Systems II: Express Briefs.

[9]  Daniela Dragomirescu,et al.  A low-power high-gain LNA for the 60 GHz band in a 65 nm CMOS technology , 2009, 2009 Asia Pacific Microwave Conference.