Multi-Commodity Flow-Based Spreading in a Commercial Analytic Placer
暂无分享,去创建一个
[1] Evangeline F. Y. Young,et al. RippleFPGA: A routability-driven placement for large-scale heterogeneous FPGAs , 2016, 2016 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).
[2] Gary William Grewal,et al. GPlace: A congestion-aware placement tool for UltraScale FPGAs , 2016, 2016 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).
[3] Vaughn Betz,et al. VPR: A new packing, placement and routing tool for FPGA research , 1997, FPL.
[4] Kia Bazargan,et al. Fast timing-driven partitioning-based placement for island style FPGAs , 2003, Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451).
[5] Marcel Gort,et al. Analytical placement for heterogeneous FPGAs , 2012, 22nd International Conference on Field Programmable Logic and Applications (FPL).
[6] R. C. Cofer,et al. Rapid System Prototyping with FPGAs: Accelerating the Design Process , 2005 .
[7] Ismail Bustany,et al. Eh?Legalizer , 2018, ACM Trans. Design Autom. Electr. Syst..
[8] Wenyi Feng,et al. Rent's rule based FPGA packing for routability optimization , 2014, FPGA.
[9] Frank M. Johannes,et al. Generic global placement and floorplanning , 1998, Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175).
[10] David T. Westwick,et al. Eh?Placer , 2016, ACM Trans. Design Autom. Electr. Syst..
[11] Tao Huang,et al. Ripple: A Robust and Effective Routability-Driven Placer , 2013, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[12] David Z. Pan,et al. UTPlaceF: A Routability-Driven FPGA Placer With Physical and Congestion Aware Packing , 2018, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[13] R. C. Cofer,et al. Rapid system prototyping with FPGAs , 2005 .
[14] Stephen Yang,et al. Clock-Aware FPGA Placement Contest , 2017, ISPD.
[15] Stephen Yang,et al. Routability-Driven FPGA Placement Contest , 2016, ISPD.
[16] Ravindra K. Ahuja,et al. Network Flows: Theory, Algorithms, and Applications , 1993 .
[17] Ismail Bustany,et al. POLAR: A High Performance Mixed-Size Wirelengh-Driven Placer With Density Constraints , 2015, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[18] Ulf Schlichtmann,et al. Kraftwerk2—A Fast Force-Directed Quadratic Placement Approach Using an Accurate Net Model , 2008, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[19] Dongjin Lee,et al. SimPL: An Effective Placement Algorithm , 2010, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[20] Elias Vansteenkiste,et al. Hierarchical Force-Based Block Spreading for Analytical FPGA Placement , 2018, 2018 28th International Conference on Field Programmable Logic and Applications (FPL).