A novel high-speed binary and gray Incrementer/Decrementer for an address generation unit

An incrementer/decrementer (INC/DEC) is a common building block in many digital systems like address generation unit which are used in microcontrollers and microprocessors. In this paper, novel architectures and designs for binary and gray INC/DECs are presented which faster than the existing ones without compromising in terms of power. The proposed architectures lay an emphasis on the usage of hybrid logic, that is, coupling of transmission gate with CMOS gates at appropriate stages for efficient design. Also, efficient utilization of the output and its complement, available in all existing implementations of gates, is done by using multiplexers in the proposed gray INC/DEC. For a 32-bit input, the proposed binary and gray INC/DEC achieve an improvement of 47%, 33% in delay and reduction of 38%, 28% in power-delay product respectively.

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