Influence of Professor T. C. Hu's Works on Fundamental Approaches in Layout

Professor T. C. Hu has made numerous pioneering and fundamental contributions in combinatorial algorithms, mathematical programming and operations research. His seminal 1985 IEEE book VLSI Circuit Layout: Theory and Design, coedited with Prof. E. S. Kuh, shaped algorithmic and optimization perspectives, as well as basic frameworks, for IC physical design throughout the following decades [44]. Indeed, Professor Hu gave a keynote address at the very first International Symposium on Physical Design, in April 1997 [41]. His research approach of (i) studying small and/or extremal cases first, (ii) always seeking to establish error bounds or other properties of heuristic outcomes (hence, always seeking to understand optimal solutions), (iii) approaching new problems from as fresh a perspective as possible, and (iv) pursuing simplicity and beauty in both formulation and exposition, has influenced generations of researchers. This paper complements [20] in recounting highlights of Professor Hu's contributions to, and impacts on, physical design. The focus is on several problems of "connection", as well as the concept of "shadow price", as they relate to layout.

[1]  Andrew B. Kahng,et al.  Optimal multi-row detailed placement for yield and model-hardware correlation improvements in sub-10nm VLSI , 2017, 2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[2]  D. Peleg,et al.  Approximating shallow-light trees , 1997, SODA '97.

[3]  Patrick H. Madden,et al.  Recursive bisection placement: feng shui 5.0 implementation details , 2005, ISPD '05.

[4]  T. C. Hu Multi-Commodity Network Flows , 1963 .

[5]  Martin D. F. Wong,et al.  Efficient network flow based min-cut balanced partitioning , 1994, ICCAD '94.

[6]  Mechthild Stoer,et al.  A Simple Min Cut Algorithm , 1994, ESA.

[7]  Andrew B. Kahng,et al.  On the performance bounds for a class of rectilinear Steiner tree heuristics in arbitrary dimension , 1992, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[8]  T. C. Hu,et al.  Optimal alphabetic trees for binary search , 1998 .

[9]  Takeshi Yoshimura,et al.  Fixed-Outline Floorplanning: Block-Position Enumeration and a New Method for Calculating Area Costs , 2008, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[10]  Andrew B. Kahng,et al.  Optimal partitioners and end-case placers for standard-cell layout , 1999, ISPD '99.

[11]  Toshihide Ibaraki,et al.  Computing Edge-Connectivity in Multigraphs and Capacitated Graphs , 1992, SIAM J. Discret. Math..

[12]  Andrew B. Kahng,et al.  Optimal robust path planning in general environments , 1993, IEEE Trans. Robotics Autom..

[13]  Andrew B. Kahng,et al.  Optimization of linear placements for wirelength minimization with free sites , 1999, Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198).

[14]  Andrew B. Kahng,et al.  A General Framework For Vertex Orderings, With Applications To Netlist Clustering , 1994, IEEE/ACM International Conference on Computer-Aided Design.

[15]  Ronald L. Graham,et al.  Tree Structures and Algorithms for Physical Design , 2018, ISPD.

[16]  Christoph Albrecht,et al.  Provably good global routing by a new approximation algorithm for multicommodity flow , 2000, ISPD '00.

[17]  T. C. Hu,et al.  BINARY TREES OPTIMUM UNDER VARIOUS CRITERIA , 1979 .

[18]  Man-Tak Shing,et al.  A decomposition algorithm for circuit routing , 1985 .

[19]  Andrew B. Kahng,et al.  RePlAce: Advancing Solution Quality and Routability Validation in Global Placement , 2019, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[20]  Chung-Kuan Cheng,et al.  A global router with a theoretical bound on the optimal solution , 1996, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[21]  Jason Cong,et al.  Provably good performance-driven global routing , 1992, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[22]  Andrew B. Kahng,et al.  Classical floorplanning harmful? , 2000, ISPD '00.

[23]  Sachin S. Sapatnekar,et al.  A practical methodology for early buffer and wire resource allocation , 2003, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[24]  G. G. Stokes "J." , 1890, The New Yale Book of Quotations.

[25]  D. F. Wong,et al.  Efficient network flow based min-cut balanced partitioning , 1994, ICCAD 1994.

[26]  T. C. Hu Letter to the Editor-On the Feasibility of Simultaneous Flows in a Network , 1964 .

[27]  K. C. Tan,et al.  Least upper bound on the cost of optimum binary search trees , 2004, Acta Informatica.

[28]  Dorothea Wagner,et al.  Modeling Hypergraphs by Graphs with the Same Mincut Properties , 1993, Inf. Process. Lett..

[29]  Jens Vygen,et al.  Worst-case ratios of networks in the rectilinear plane , 2001, Networks.

[30]  Chung-Kuan Cheng,et al.  Linear decomposition algorithm for VLSI design applications , 1995, Proceedings of IEEE International Conference on Computer Aided Design (ICCAD).

[31]  Chris C. N. Chu,et al.  DeFer: Deferred Decision Making Enabled Fixed-Outline Floorplanning Algorithm , 2010, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[32]  Josephus Hulshof,et al.  Optimal Flood Control , 2012 .

[33]  Andrew B. Kahng,et al.  Multiway partitioning via geometric embeddings, orderings, and dynamic programming , 1995, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[34]  Andrew B. Kahng,et al.  Timing-driven Steiner trees are (practically) free , 2006, 2006 43rd ACM/IEEE Design Automation Conference.

[35]  D. Greene,et al.  Multi-Way Partitioning Via Geometric Embeddings, Orderings, and Dynamic Programming , 1995 .

[36]  Frank Thomson Leighton,et al.  An approximate max-flow min-cut theorem for uniform multicommodity flow problems with applications to approximation algorithms , 1988, [Proceedings 1988] 29th Annual Symposium on Foundations of Computer Science.

[37]  Chaomin Luo,et al.  Large-scale fixed-outline floorplanning design using convex optimization techniques , 2008, 2008 Asia and South Pacific Design Automation Conference.

[38]  Jens Vygen,et al.  BonnPlace: Placement of Leading-Edge Chips by Advanced Combinatorial Algorithms , 2008, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[39]  T. C. Hu Letter to the Editor---The Maximum Capacity Route Problem , 1961 .

[40]  Chung-Kuan Cheng,et al.  Linear placement algorithms and applications to VLSI design , 1987, Networks.

[42]  R. Prim Shortest connection networks and some generalizations , 1957 .

[43]  T C Hu,et al.  Solution of the discrete Plateau problem. , 1992, Proceedings of the National Academy of Sciences of the United States of America.

[44]  Sachin S. Sapatnekar,et al.  A practical methodology for early buffer and wire resource allocation , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).

[45]  Edsger W. Dijkstra,et al.  A note on two problems in connexion with graphs , 1959, Numerische Mathematik.

[46]  Andrew B. Kahng,et al.  Can recursive bisection alone produce routable, placements? , 2000, Proceedings 37th Design Automation Conference.

[47]  Yoji Kajitani,et al.  Fixed-outline floorplanning with constraints through instance augmentation , 2005, 2005 IEEE International Symposium on Circuits and Systems.

[48]  Atchutananda Surampudi,et al.  An Energy Efficient Spectrum Sensing in Cognitive Radio Wireless Sensor Networks , 2017, ArXiv.

[49]  Andrew B. Kahng,et al.  Floorplan evaluation with timing-driven global wireplanning, pin assignment, and buffer/wire sizing , 2002, Proceedings of ASP-DAC/VLSI Design 2002. 7th Asia and South Pacific Design Automation Conference and 15h International Conference on VLSI Design.

[50]  Man-tak Shing,et al.  A decomposition algorithm for multi-terminal networks flows , 1986, Discret. Appl. Math..

[51]  Georg Sigl,et al.  GORDIAN: VLSI placement by quadratic programming and slicing optimization , 1991, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[52]  Jason Cong,et al.  Edge separability-based circuit clustering with application to multilevel circuit partitioning , 2004, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[53]  T. C. Hu,et al.  Multi-Terminal Network Flows , 1961 .

[54]  W. A. Horn Single-Machine Job Sequencing with Treelike Precedence Ordering and Linear Delay Penalties , 1972 .

[55]  Igor L. Markov,et al.  Fixed-outline floorplanning: enabling hierarchical design , 2003, IEEE Trans. Very Large Scale Integr. Syst..

[56]  D. Adolphson Optimal linear-ordering. , 1973 .

[57]  Josef Kittler,et al.  Combinatorial Algorithms , 2016, Lecture Notes in Computer Science.

[58]  T. C. Hu Optimum Communication Spanning Trees , 1974, SIAM J. Comput..

[59]  J. David Morgenthaler,et al.  Optimal Integer Alphabetic Trees in Linear Time , 2005, ESA.

[60]  De-Sheng Chen,et al.  Fixed-outline floorplanning through evolutionary search , 2004 .

[61]  Qian Wang,et al.  An improved cerebral vessel extraction method for MRA images. , 2015, Bio-medical materials and engineering.

[62]  E.S. Kuh,et al.  PROUD: a sea-of-gates placement algorithm , 1988, IEEE Design & Test of Computers.

[63]  David Z. Pan,et al.  Triple Patterning Aware Detailed Placement Toward Zero Cross-Row Middle-of-Line Conflict , 2017, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[64]  Michael Elkin,et al.  Narrow-Shallow-Low-Light Trees with and without Steiner Points , 2011, SIAM J. Discret. Math..

[65]  Yuelin Du,et al.  Optimization of standard cell based detailed placement for 16 nm FinFET process , 2014, 2014 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[66]  Derong Liu,et al.  Prim-Dijkstra Revisited: Achieving Superior Timing-driven Routing Trees , 2018, ISPD.

[67]  Gary K. Moy A Specific Network Link and Path Likelihood Prediction Tool. , 1996 .

[68]  Chang-Tzu Lin,et al.  Robust fixed-outline floorplanning through evolutionary search , 2004, ASP-DAC.

[69]  David R. Karger,et al.  Prim-Dijkstra tradeoffs for improved performance-driven routing tree design , 1995, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[70]  Andrew B. Kahng,et al.  A general framework for vertex orderings with applications to circuit clustering , 1996, IEEE Trans. Very Large Scale Integr. Syst..

[71]  Chung-Kuan Cheng,et al.  A replication cut for two-way partitioning , 1995, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[72]  David Z. Pan,et al.  MrDP: Multiple-row detailed placement of heterogeneous-sized cells for advanced nodes , 2016, 2016 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).