Analysis of buffered hybrid structured clock networks

This paper presents a novel approach for fast transient analysis of buffered hybrid structured clock networks. The new method applies structure reduction and relaxed hierarchical analysis methods to reduce the circuit complexity and speedup the simulation. A simple controlled sources model is used for modeling clock buffers to deal with nonlinearity in the buffered clock trees. Our experiment results show that the proposed algorithm is about two orders of magnitude faster than HSPICE without loss on accuracy and stability. The relatively errors on delay times are within a few percent of the exact ones.

[1]  Y. Yamada,et al.  Equivalent waveform propagation for static timing analysis , 2004, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[2]  Andrew B. Kahng,et al.  Zero-skew clock routing trees with minimum wirelength , 1992, [1992] Proceedings. Fifth Annual IEEE International ASIC Conference and Exhibit.

[3]  J. Jensen,et al.  Sizing of clock distribution networks for high performance CPU chips , 1996, 33rd Design Automation Conference Proceedings, 1996.

[4]  Sachin S. Sapatnekar,et al.  Hybrid structured clock network construction , 2001, IEEE/ACM International Conference on Computer Aided Design. ICCAD 2001. IEEE/ACM Digest of Technical Papers (Cat. No.01CH37281).

[5]  Yehea I. Ismail.  Improved model-order reduction by using spacial information in moments , 2003, IEEE Trans. Very Large Scale Integr. Syst..

[6]  Yici Cai,et al.  A fast delay analysis algorithm for the hybrid structured clock network , 2004, IEEE International Conference on Computer Design: VLSI in Computers and Processors, 2004. ICCD 2004. Proceedings..

[7]  Charlie Chung-Ping Chen,et al.  Future SoC design challenges and solutions , 2002, Proceedings International Symposium on Quality Electronic Design.

[8]  Rajendran Panda,et al.  Hierarchical analysis of power distribution networks , 2000, DAC.

[9]  Anthony Vannelli,et al.  Interconnection modelling using distributed RLC models , 2003, The 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications, 2003. Proceedings..

[10]  Charlie Chung-Ping Chen,et al.  Efficient large-scale power grid analysis based on preconditioned Krylov-subspace iterative methods , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).

[11]  Lawrence T. Pileggi,et al.  Asymptotic waveform evaluation for timing analysis , 1990, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[12]  Alina Deutsch,et al.  Designing the best clock distribution network , 1998, 1998 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.98CH36215).

[13]  Lawrence T. Pileggi,et al.  PRIMA: passive reduced-order interconnect macromodeling algorithm , 1997, ICCAD 1997.

[14]  K.A. Jenkins,et al.  A clock distribution network for microprocessors , 2000, 2000 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.00CH37103).