A Study of Relaxation Current in

Dielectric relaxation currents in SiO Al O and SiO HfO high- dielectric stacks are studied in this paper. We studied the thickness dependence, gate voltage polarity depen- dence and temperature dependence of the relaxation current in high- dielectric stacks. It is found that high- dielectric stacks show different characteristics than what is expected based on the dielectric material polarization model. By the drain current variation measurement in n-channel MOSFET, we confirm that electron trapping and detrapping in the high- dielectric stacks is the cause of the dielectric relaxation current. From substrate injection experiments, it is also concluded that the relaxation current is mainly due to the traps located near the SiO /high- interface. As the electron trapping induces a serious threshold voltage shift problem, a low trap density at the SiO /high- inter- face is a key requirement for high- dielectric stack application and reliability in MOS devices.

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