A dynamic-SDRAM-mode-control scheme for low-power systems with a 32-bit RISC CPU

We have developed a dynamic-SDRAM-mode-control scheme for low-power systems with a 32-bit RISC CPU. The scheme is based on two dynamic changes of SDRAM modes: from active standby to standby and from standby to active standby. It reduces both the operating current and the latency of an SDRAM. An analysis using benchmark programs shows that the developed scheme reduces the SDRAM operating current by 40% and latency by 38% compared to those of standby mode. An SDRAM controller was developed based on this scheme and 0.18 /spl mu/m CMOS technology. The area of the controller is 0.28 mm/sup 2/ and its operating current is 2.5 mA at 1.8 V and 100 MHz.

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