Fast triggering in high-energy physics experiments using hardware neural networks

High-energy physics experiments require high-speed triggering systems capable of performing complex pattern recognition at rates of Megahertz to Gigahertz. Neural networks implemented in hardware have been the solution of choice for certain experiments. The neural triggering problem is presented here via a detailed look at the H1 level 2 trigger at the HERA accelerator, Hamburg, Germany, followed by a section on the importance of hardware preprocessing for such systems, and finally some new architectural ideas for using field programmable gate arrays in very high-speed neural-network triggers at upcoming experiments.

[1]  S. Udluft,et al.  Hardware preprocessing for the H1-Level 2 neural network trigger upgrade , 2002 .

[2]  Jean-Christophe Prévotet,et al.  Etude des systèmes électroniques pour les réseaux connexionnistes appliqués à l'instrumentation en temps-réel , 2002 .

[3]  Patrick Garda,et al.  Hardware solutions for implementation of neural networks in High Energy Physics triggers , 2002, The European Symposium on Artificial Neural Networks.

[4]  M. Haase,et al.  DOLFIN-digit online for integration neural networks , 2000, 2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353).

[5]  Tughrul Arslan,et al.  IEEE International Symposium on Circuits and Systems (ISCAS 2000) , 2000 .

[6]  A. Donnachie,et al.  Charm production at HERA , 1999, hep-ph/9910262.

[7]  Bertrand Granado Architecture des systemes electroniques pour les reseaux de neurones. Conception d'une retine connexionniste , 1998 .

[8]  J. Fent,et al.  Realization of a second level neural network trigger for the H1 experiment at HERA , 1997 .

[9]  Emile Fiesler,et al.  Neural Network Adaptations to Hardware Implementations , 1997 .

[10]  Brian Kingsbury,et al.  Spert-II: A Vector Microprocessor System , 1996, Computer.

[11]  K. Burkett,et al.  Performance of the CDF neural network electron isolation trigger at Fermilab , 1995 .

[12]  E. Barrelet,et al.  The H1 detector at HERA , 1996 .

[13]  Ulrich Ramacher,et al.  SYNAPSE - A Neurocomputer that Synthesizes Neural Algorithms on a Parallel Systolic Engine , 1992, J. Parallel Distributed Comput..

[14]  Lawrence D. Jackel,et al.  An analog neural network processor with programmable topology , 1991 .

[15]  Naofumi Takagi,et al.  Design of high speed MOS multiplier and divider using redundant binary representation , 1987, 1987 IEEE 8th Symposium on Computer Arithmetic (ARITH).

[16]  Milos D. Ercegovac,et al.  On-Line Arithmetic: An Overview , 1984, Optics & Photonics.

[17]  Milos D. Ercegovac,et al.  On-Line Algorithms for Division and Multiplication , 1977, IEEE Transactions on Computers.

[18]  Kishor S. Trivedi,et al.  On-line algorithms for division and multiplication , 1975, 1975 IEEE 3rd Symposium on Computer Arithmetic (ARITH).