A current-mode continuous-time /spl Sigma//spl Delta/ modulator with delayed return-to-zero feedback

In this paper, a design method for continuous-time /spl Sigma//spl Delta/ modulators with RZ feedback pulse is proposed. This method is used to design a second-order continuous-time /spl Sigma//spl Delta/ modulator. The circuit is realized using continuous-time current-mode integrators and switched-current sources DAC. The effect of the integrator thermal noise and nonideal RZ feedback pulse on the system performance is studied. An analog layout language was used to generate the complete layout of the modulator in a 0.6 /spl mu/m CMOS process. With a sampling frequency of 28 MHz, the circuit is expected to achieve 80 dB of dynamic range for a 200 kHz bandwidth input signal. The circuit operates from a power supply of /spl plusmn/1.65 V with a power consumption of 9.1 mW and occupies an area of 0.348 mm/sup 2/.

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