A 1.2V 30mW 8b 800MS/s time-interleaved ADC in 65nm CMOS

An 8-bit 800 MS/s time-interleaved pipeline ADC with SNDR of 47.8 dB and 44.2 dB for 1 MHz and 400 MHz inputs is presented. The techniques of sub-ADC preamp sharing and reference voltage buffer current-reusing are proposed to minimize power consumption. The ADC implemented in 65 nm digital CMOS process with an active area of 0.12 mm2 consumes 30 mW from a 1.2 V supply and achieves a FOM of 0.28 pJ/conversion-step.