MVSIS 2 . 0 Programmer ’ s Manual

MVSIS is a logic synthesis system, which enhances traditional binary logic synthesis with capabilities related to multi-value logic. This manual introduces the programming environment of MVSIS 2.0 and compares it with those of SIS 1.3 and VIS 1.4. The new data structures are described and the motivation behind them is explained. The goal is to help the reader with the general understanding of logic synthesis and the working knowledge of C programming get started writing his or her own application code, which manipulates binary or MV networks in MVSIS.

[1]  P. R. Stephan,et al.  SIS : A System for Sequential Circuit Synthesis , 1992 .

[2]  Malay K. Ganai,et al.  Robust Boolean reasoning for equivalence checking and functional property verification , 2002, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[3]  Alberto L. Sangiovanni-Vincentelli,et al.  Multiple-Valued Minimization for PLA Optimization , 1987, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[4]  Robert K. Brayton,et al.  Simplification of non-deterministic multi-valued networks , 2002, IEEE/ACM International Conference on Computer Aided Design, 2002. ICCAD 2002..