Compiler support for reducing leakage energy consumption
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[1] T. Ghani,et al. Effectiveness of reverse body bias for leakage control in scaled dual Vt CMOS ICs , 2001, ISLPED'01: Proceedings of the 2001 International Symposium on Low Power Electronics and Design (IEEE Cat. No.01TH8581).
[2] Shin'ichiro Mutoh,et al. 1-V power supply high-speed digital circuit technology with multithreshold-voltage CMOS , 1995, IEEE J. Solid State Circuits.
[3] Miodrag Potkonjak,et al. MediaBench: a tool for evaluating and synthesizing multimedia and communications systems , 1997, Proceedings of 30th Annual International Symposium on Microarchitecture.
[4] Narayanan Vijaykrishnan,et al. Evaluating run-time techniques for leakage power reduction , 2002, Proceedings of ASP-DAC/VLSI Design 2002. 7th Asia and South Pacific Design Automation Conference and 15h International Conference on VLSI Design.
[5] Farid N. Najm,et al. A gate-level leakage power reduction method for ultra-low-power CMOS circuits , 1997, Proceedings of CICC 97 - Custom Integrated Circuits Conference.
[6] Santosh Pande,et al. Optimizing Static Power Dissipation by Functional Units in Superscalar Processors , 2002, CC.
[7] Steven S. Muchnick,et al. Advanced Compiler Design and Implementation , 1997 .
[8] Tughrul Arslan,et al. Proceedings Design, Automation and Test in Europe Conference and Exhibition , 2003, 2003 Design, Automation and Test in Europe Conference and Exhibition.