Reliable SoC Design and Implementation of SHA-3-HMAC Algorithm with Attack Protection

The Keyed-Hash Message Authentication Codes (HMAC) is a widely used method to ensure the integrity and authentication of data and its security is based on the Hash encryption algorithm. As part of HMAC, the secure hash algorithm (SHA)-3 was selected as the winner of the hash function competition in 2012. Though SHA-3 has been implemented individually in hardware, reliable SoC (system on a chip) design with multiple attack protection is still unsolved to support SHA-3-HMAC. In this paper, we propose our design of a SHA-3-HMAC SoC module which has the ability to defend against common side channel attacks and error injection attacks. Our design also supports different digest values of 256/384/512 according to configuration, with automatic padding operation inside SHA-3. Furthermore, through application-specific integrated circuit (ASIC) analysis of the implementation of our design, the maximum clock frequency of our implementation can reach 300MHz. By adding a clock randomization module and a circuit design based on time redundancy, the security and reliability of the SoC module has been greatly improved.

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