Design and implementation of moment invariants for pattern recognition in VLSI (very large scale integration)

This paper describes the design of a very large scale integration (VLSI) application specific integrated circuit (ASIC) for use in pattern recognition. The pattern recognition scheme uses Hu and Maitra's algorithms for moment invariants. A prototype design was generated that resolved the long delay time of the multiplier by custom designing adder cells based on the Manchester carry chain. Use of the Manchester carry chain effectively incorporated the lookahead carry function into the adder cells. The prototype ASIC is currently being fabricated in 2.0-mm compiled simulator for metal oxide semiconductor (CMOS) technology (simulated at 20 MHz). The prototype consisted of a 4 {times} 8 multiplier and a 12-bit accumulator stage. The present ASIC design consists of a 9 {times} 26 multiplier (maximum propagation time of 50 ns) and a 48-bit accumulator stage. The final ASICs will be used in parallel at the board level to achieve the 56 MegaPixels/s (230 million operations per second (MOPs)) necessary to perform the moment invariant algorithms in real time on 512 {times} 512 pixel images with 256 grey scales. 11 refs., 3 figs., 7 tabs.