A Novel Method for Computing Exponential Function Using CORDIC Algorithm

In this paper, design of Coordinate Rotation Digital Computer (CORDIC) based 2D Gaussian function and an efficient Very Large Scale Integration (VLSI) architecture suitable for Field Programmable Gate Array (FPGA) implementation is presented. The potential application of the proposed 2D Gaussian function includes image enhancement, smoothing, edge detection, filtering etc. The proposed algorithm uses expanded range of CORDIC algorithm since the conventional technique converges within the range of [-1.12, +1.12]. The architectures developed exploits high degrees of pipelining and parallel processing in order to achieve real time performance. The design has been realized using Register Transfer Language (RTL) compliant Verilog code and fits into a single chip with a gate count utilization of 75,151. The algorithm has been tested for Gaussian based image smoothening application and is implemented on XC2V1000-6bg575 Xilinx FPGA device. The architecture developed is capable of processing one pixel per clock cycle and provides results in real time. The experimental results shows that the proposed approach exhibits better performance when compared with the other researcher methods.

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