Hardware implementation of the LDPC decoder in the FPGA structure

The paper proposes hardware implementation of the LDPC decoder (Low Density Parity Check) as a serial architecture in the FPGA structure. The implemented decoder has 4-bit Log-Likelyhood Ratio messages precision and is dedicated for regular (3,6) code with 512 x 1024 parity check matrix. In order to reduce the complexity, the proposed decoder uses Min-Sum algorithm for check nodes (CNUs). In this article we present Bit Error Rate results that prove correctness of the decoder operation implemented in the Intel Cyclone IV. We also estimate power consumption of this implementation.